CAT28F102-12 Datasheet



Features, Applications
s Fast Read Access Time: ns s Low Power CMOS Dissipation:

x 16 Word Organization s Stop Timer for Program/Erase s On-Chip Address and Data Latches s JEDEC Standard Pinouts:

�Active: 30 mA max (CMOS/TTL levels) �Standby: 1 mA max (TTL levels) �Standby: 100 �A max (CMOS levels)

s 100,000 Program/Erase Cycles s 10 Year Data Retention s Electronic Signature

The is a high speed x 16-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. It is pin and Read timing compatible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F102 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP packages.

2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply No Connect

Temperature Under Bias................. to +105�C Storage Temperature....................... to +150�C Voltage on Any Pin with Respect �0.6V to +VCC + 2.0V Voltage on Pin A9 with Respect to +13.5V VPP with Respect to Ground during to +14.0V VCC with Respect to +7.0V Package Power Dissipation Capability (TA 1.0 W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS Symbol NEND

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Parameter Endurance Data Retention ESD Susceptibility Latch-Up

Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17

Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance

Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V.



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