I High speed operation: 3MHz I Low power CMOS technology to 5.5 volt operation I Selectable or x16 memory organization I Self-timed write cycle with auto-clear I Hardware and software write protection I Power-up inadvertant write protection I Sequential read I Program enable (PE) pin I 1,000,000 Program/erase cycles I 100 year data retentionDESCRIPTION
The a 16K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86 is manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, 8-pin SOIC and 8-pad TDFN packages.
Pin Name CS Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization Program Enable
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.� Catalyst Semiconductor, Inc. Characteristics subject to change without notice.
Temperature Under Bias.................. to +125�C Storage Temperature........................ to +150�C Voltage on any Pin with Respect -2.0V to +VCC +2.0V VCC with Respect to Ground................ to +7.0V Package Power Dissipation Capability (TA 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS
Symbol VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min Typ Max Units Cycles/Byte Years Volts mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.D.C. OPERATING CHARACTERISTICS VCC to +5.5V, unless otherwise specified.
Symbol ISB1 ISB2 ILI ILO VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 0V ORG=GND CS=0V ORG=Float or VCC VIN 0V to VCC VOUT 0V to VCC, 0V 4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC 4.5V 1.8V VCC < 4.5V VCC < 5.5V IOL 2.1mA 4.5V VCC < 5.5V IOH -400�A 1.8V VCC < 4.5V IOL 1mA 1.8V VCC < 4.5V IOH = -100�A VCC 0.7 0 Min Typ Max VCC + 1 VCC VCC+1 0.4 Units mA �A
Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V.Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG)
Data x8 x16 Comments Read Address AN� A0 Clear Address AN� A0 D15-D0 Write Address AN� A0 Write Enable Write Disable Clear All Addresses D7-D0 D15-D0 Write All AddressesInstruction READ ERASE WRITE EWEN EWDS ERAL WRAL
A.C. CHARACTERISTICS Limits VCC = 1.8V-5.5V Symbol tCSS tCSH tDIS tDIH tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency 100pF (3) Test Conditions Min DC Max VCC = 2.5V-5.5V Min Max VCC = 4.5V-5.5V Min Max Units ms �s kHz