CB-C8VM Datasheet

Standard Cell


Features, Applications

NEC's CB-C8VX/VM CMOS cell-based ASIC family facilitates the design of complete cell-based silicon systems composed of user-defined logic, complex macrofunctions such as microprocessors, intelligent peripherals, analog functions, and compiled memory blocks. The CB-C8VX cell-based ASIC series employs 0.5-micron (0.35-micron effective) silicon gate CMOS process with silicidation. This advanced process greatly reduces the number of contacts per cell, leading to areaefficient library elements optimized on speed with a 3.3volt power supply. CB-C8VM, a derivative of CB-C8VX, features a unique I/O structure that provides a full 5-volt CMOS interface. For both technologies, the TitaniumSilicide process results in overall reduced power consumption per cell. Combining very high integration, high speed, and low power consumption, this technology meets today's rigorous application demands. Fully supported by NEC's sophisticated OpenCAD design framework, CB-C8VX/VM maximizes design quality and flexibility while minimizing ASIC design time. NEC's OpenCAD system combines popular third-party design tools with proprietary NEC tools, including advanced floorplanner and clock tree synthesis tools.

CB-C8VM offers a full voltage swing interface a 5-volt CMOS signal environment. This option is realized by implementing a section of thicker gate oxide into the I/O buffer to guarantee the necessary breakdown voltages. The 5-volt I/O buffers can be placed at any location of the I/O area and are freely mixable with 3.3-volt buffers. The internal core is identical to CB-C8VX.

CB-C8VX/VM Series Features 0.5-micron (drawn), Ti-Silicide CMOS technology True 3.3 V process 36 base sizes, each with 2- and 3-metal layer options Usable gates from to 703K gates True 5 V CMOS interface by multi-oxide I/O structure Staggered pad ring for high gate-to-pad ratio 5 V and 3.3 V PCI buffer, including 66-MHz PCI GTL and HSTL buffer in development Low power dissipation: 1.04 mW/MHz/gate (3.3 V) Extensive macro range (CPUs, peripherals, analog) Memory compiler for various types of memory blocks Extensive package support: PQFP, TQFP, BGA, TBGA Automatic clock skew control by clock tree synthesis OpenCAD: popular, third-party CAE tools supported

CB-C8VX/VM Series Benefits High-density cell structure High speed at low power supply Flexible base sizes to best fit design needs High integration capabilities Supports flexible interfacing to different signal voltages Minimizes device cost for high I/O requirement Full PCI support compliant with latest PCI specification High-speed I/F to memory and processor buses Ideally-suited for hand-held applications Advanced system-on-silicon capabilities Area-effective memory integration on chip Delivers the latest package requirements Minimizes on-chip clock skew Smooth design flow from customer design to silicon

CB-C8VX supports both 3.3-volt and 5-volt-tolerant signaling. The 5-volt-tolerant buffers enable CB-C8VX devices to communicate with 5-volt TTL signals while protecting the ASIC. CB-C8VX requires only a 3.3-volt power supply. Each of these blocks has several different drive strengths, allowing the synthesis tool to select the most suitable block for the required internal load. This generally reduces the design overhead without influencing design performance. The internal gate delay for a two-input NAND gate is 110 picoseconds (ps), (F/O=1, L=0mm) and 220 ps under loaded conditions L=2mm). To meet today's high-speed demands, high-performance I/O macros are mandatory. CB-C8VX/VM supports macros such as GTL and HSTL for fast, lowpower data transfer, PLLs to synchronize on-chip system clocks, and PCI signaling standards. Also, CB-C8VX/VM offers a variety of macrofunctions to be incorporated on a single chip. These macrofunctions include CPU cores, peripheral devices, RAM/ROM and analog functions, enabling designers to create systems on silicon.

Gate complexities to 703K usable gates can be integrated on the largest of 36 die sizes, each routable with or 3-metal layers. This gives enough flexibility to optimally fit design needs. Twenty-two die sizes offer a single I/O pad ring and 14 are equipped with a staggered dual pad ring in order to achieve a high padto-gate ratio. For details, please refer to Table 2 and Table 3. The family offers an extensive library of primitive macrofunctions characterized for 3.3-volt operation.

NEC's CB-C8VX/VM Ti-Silicide process features exceptionally low power dissipation to facilitate highspeed operation without the need of costly package options, and drastically increases battery life for handheld applications. At 3.3-volts, power dissipation for internal cells is 1.04 �W/gate/MHz.

Single pad ring die steps. (1) Glue logic only, with average utilization.
Dual pad ring die steps. (1) Glue logic only, with average utilization.

For those systems not yet ready to migrate completely 3.3-volts, CB-C8 has a full 5-volt CMOS interface available. Applying two additional process steps that realize a "multi-oxide" section in the I/O area, 5-volt speed and drive capabilities are available with the help of a separate 5-volt supply rail. The 5-volt I/O buffers include level shifters to convert the 5-volt signal levels to the internal core supply voltage of 3.3-volts. This CB-C8 derivative is called CB-C8VM and is, except for the different I/O structure, identical to CB-C8VX. For moderate speed and driveable 5-volt I/O cell requirements, CB-C8VM's flexibility provides tolerant I/Os that safely interface to 5V devices using a single 3.3volt power supply. In both cases, the 3.3-volt and 5-volt interfaces can be mixed without restriction along the entire I/O ring.

NEC offers a wide selection of CPU/MCU cores, industrystandard intelligent peripheral macros, and compilable RAM/ROM blocks as well as analog functions in hard macro form that can be integrated onto a single CBC8VX/VM chip. Including such macrofunctions in an ASIC design makes it possible to achieve a high level of integration, performance, and system security. The range of NEC's on-chip macrofunctions includes NEC's proprietary 32-bit V810TM RISC CPU, and an upgraded high-speed version of the popular 16-bit CPU V30HLTM, called V30MXTM, which operates at clock speeds of 33 MHz at 3.3-volts, and offers an improved 286-compatible address pipelining and uses a 24-bit address bus. Other specific cores can be implemented on request. For details about the full range of on-chip macrofunctions, refer to Table 4. Embedded macrofunctions are easy to place, route, and simulate. Because these macros are derived from NEC's standard parts, they have fully characterized parameters and can be tested with standard test vectors to ensure full functionality and reliability. NEC's test bus architecture allows complete system simulation, production testing of the internal circuits of the macrofunctions, and seamless embedded CPU core emulation. The CPU may be connected externally and can be replaced by an in-circuit emulator (ICE). All this is performed with only two dedicated test control pins.

CB-C8VX Device Names Interface options �PD97xxx true 5 V tolerant 3.3 V

V30MX: 16-bit microprocessor (16-bit data bus, 33 MHz) V810TM: 32-bit RISC microprocessor (25 MHz) Programmable DMA controller (4 channels, 20 MHz) USART: serial data control (full-duplex Tx/Rx, 300kbit/s, 20 MHz) Programmable timer/counter (16-bit, 3 counter, 6 modes, 20 MHz) Programmable parallel interface (8-bit, 3 I/O ports, 3 modes) Programmable interrupt control (64 interrupt request inputs) 8-bit parallel I/O real-time clock Single-double density floppy disk controller HDLC Controller: Full duplex, Baud rate 4 Mbps, built-in DMA I2 C Bus interface: receive, transmit, master and slave UART: for PC-compatible serial ports UART with FIFO: for PC-compatible serial ports

is a trademark of Zilog, Inc. V30HL, V30MX and v810 are trademarks of NEC Corporation is a trademark of Philips



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