HomedatasheetCB-C9

CB-C9 Datasheet

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Description

NEC's CB-C9 CMOS cell-based ASIC family facilitates the design of complete cell-based silicon systems composed of user-defined logic, complex macrofunctions such as microprocessors, intelligent peripherals, analog functions, and compiled memory blocks. The CB-C9 cell-based ASIC series employs 0.35micron (0.27-micron effective) silicon gate CMOS process with silicidation. This advanced process greatly reduces the number of contacts per cell, leading to area-efficient library elements optimized on speed with a 3.3-V power supply. CB-C9 achieves 1.6M usable gates. A library option for 2.5-V power supply voltage is being developed. For this technology, the Titanium-Silicide process results to 30% reduced power consumption per cell, compared 0.5-micron 3.3-V technologies. Combining very high integration, super high-speed, and low power consumption, this technology meets today's high-performance application demands. Fully supported by NEC's sophisticated OpenCAD � design framework, CB-C9 maximizes design quality and flexibility while minimizing ASIC design time.

NEC's OpenCAD system combines popular third-party design tools with proprietary NEC tools, including advanced floorplanner and clock tree synthesis tools.

CB-C9 Family Features 0.35-micron (drawn), Ti-Silicide CMOS technology 3.3-V operation (2.5-V in development) 26 base sizes, each with 2- and 3-metal layer options Usable gates from to 1.6M gates Level shifter I/O: 3.3-V external to 2.5-V internal Three pad ring options for high gate to pad ratio PCI buffer, including 66 MHz PCI GTL, HSTL, pECL buffer support Low power dissipation: 0.7 �W/MHz/gate (3.3-V), 0.5 �W/MHz/gate (2.5-V) Extensive macro selection (CPUs, peripherals, analog) Datapath compiler for various types of ALU, multiplier, adder Memory compiler for various types of memory blocks Extensive package support: PQFP, BGA, TBGA, CSP Automatic clock skew control by clock tree synthesis Popular, third-party CAE tools CB-C9 Family Benefits High-density cell structure Super high-speed at low power supply Flexible base sizes to best fit design needs Super high integration capabilities Supports flexible interfacing to different signal voltages Minimizes device cost for high I/O requirement PCI support compliant with latest PCI specification High-speed I/F to memory and processor buses Ideally-suited for hand-held applications Supports advanced system-on-silicon design Speed & area-effective memory modules Area-effective memory integration on-chip Delivers the latest package requirements Minimizes on-chip clock skew Smooth design flow from customer design to silicon

CB-C9 supports both 3.3-V and 5-V-tolerant signaling. The 5-V-tolerant buffers enable CB-C9 devices to communicate to 5-V TTL signal while protecting the ASIC. If 5-V-tolerant buffers are not required, 3.3-V buffers may be substituted, thus increasing the die area available for logic.

Gate complexities to 1.6M usable gates can be integrated on the largest of 26 die sizes, each routable with or 3-metal layers. This gives enough flexibility to optimally fit design needs. Three I/O ring options: a single I/O pad ring (type S); or two pitches of dual pad ring (types C and T). For details, please refer to Table 2.

N = The number of sides which are composed of only 3V I/F buffers

The family offers an extensive library of primitive macrofunctions characterized for 3.3-V operation (2.5V operation in the future). Each of these blocks has several different drive strengths, allowing the synthesis tool to select the most suitable block for the required internal load. This generally reduces the design overhead without influencing design performance. The internal gate delay for a two-input NAND gate is 87 picoseconds (ps), L=0mm, 3.3-V operation) and under loaded conditions 113 (F/O=2, L=typ, 3.3-V operation) and ps (F/O=1, L=typ, 2.5-V operation). To meet today's high-speed demands, high-performance I/O macros are mandatory. CB-C9 supports macros such as GTL, pECL, and HSTL for fast, low power data transfer, PLLs to synchronize on-chip system clocks, and PCI signaling standards. Also, CB-C9 offers a variety of macrofunctions to be incorporated on a single chip. These macrofunctions include CPU cores, peripheral devices, RAM/ROM, datapath macros and functions, enabling designers to perform system-on-silicon. Moreover, level shifters (connect between 3.3-V external and 2.5-V internal) are supported to provide low power consumption and flexible interfacing to different signal voltages making correspondence. The range of NEC's proprietary 32-bit RISC CPUs include V810, V851 which has V810 core and 16-bit external data bus, and an upgraded high-speed version of the popular 16-bit CPU V30MX, which operates at clock speeds of 33 MHz at 3.3-V, and offers an improved 286-compatible address pipelining and uses a 24-bit address bus. Other specific cores can be implemented on request. For details about the full range of on-chip macrofunctions, refer to Table 3. Please also refer to Table 4 for compiled RAM specifications. Embedded macrofunctions are easy to place, route, and simulate. Because these macros are derived from NEC's standard parts, they have fully characterized parameters and can be tested with standard test vectors to ensure full functionality and reliability. NEC's test bus architecture allows complete system simulation, production testing of the internal circuits of the macrofunctions, and seamless embedded CPU core emulation. The CPU may be connected externally and can be replaced by an in-circuit emulator (ICE). All this is performed with only two dedicated test control pins.

Major advantages of NEC's CB-C9 ASIC family are high integration density, high speed and very low power consumption and cost-effective memory and megamacro integration. Following these main advantages results in a wide range of applications. For example, high-performance transmission and switching systems, based on ATM technique, may take advantage from high speed, high integration density and high performance memory integration. High-end hand-held applications as PDA's or mobile communication equipment make use of low power and the capability of global system integration including powerful microprocessor cores, which results in small system cases. Future high-end consumer products such as digital TV set-top boxes need system-on-silicon integration to allow cost-effective mass production. High-end chipsets for engineering workstations (EWS) or graphic PC-subsystems need very high performance combined with cost-effective packaging solutions. With it's very low power consumption, NEC's CB-C9 family enables the usage of more cost-effective packaging solutions.

NEC's CB-C9 Titanium-Silicide process features exceptionally low power dissipation to facilitate super high-speed operation without the need of costly package options. The process also drastically increases battery life for hand-held applications. The new ASIC family dissipates power at 0.7 �W/MHz/gate (3.3-V) and at 0.5 �W/MHz/gate (2.5-V).

To test the logical circuit of 1.6M gate large-scale easily, CB-C9 allows use of Scan and Boundary Scan for logic area, BIST for memory macros, and direct accessed test bus architecture for core macros.

NEC offers a wide selection of CPU/MCU cores, industry-standard intelligent peripheral macros, and compilable RAM/ROM blocks and datapath macros as well as analog functions in hard macro form that can be integrated onto a single CB-C9 chip. Including such macrofunctions in an ASIC design makes it possible to achieve a high level of integration, performance, and system security.


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