|Complete VCXO Based Phase Lock Loop
x 2 mm, smallest VCXO PLL available Output Frequencies to 65.536 MHz or 3.3 Vdc operation Tri-State Output Loss of Signal Alarm VCXO with CMOS outputs �40/85 �C temperature rangeApplications
Frequency Translation Clock Smoothing, Clock Switching NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical Switching/Routing, Base Station
The is a user-configurable crystal based PLL integrated circuit. It includes a digital phase detector, op-amp, VCXO and additional integrated functions for use in digital synchronization applications. Loop filter software is available as well SPICE models for circuit simulation.
Table 1. Electrical Performance Parameter Output Frequency (ordering option) 5.0 V option 3.3 V option 1 Supply Voltage +5.0 +3.3 Supply Current Output Logic Levels 2 Output Logic High 2 Output Logic Low Output Transition Times 2 Rise Time 2 Fall Time Input Logic Levels 2 Output Logic High 2 Output Logic Low Loss of Signal Indication 2 Output Logic High 2 Output Logic Low Nominal Frequency on Loss of Signal Output 1 Output 2 3 Symmetry or Duty Cycle Out 1 Out 2 RCLK Absolute Pull Range (ordering option)over operating temperature, aging, and power supply variations
Test Conditions for APR (+5.0 V option) Test Conditions for APR (+3.3 V option) Gain Transfer Phase Detector Gain +5V option +3.3V option Operating temperature (ordering option) Control Voltage Leakage Current
A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded). 2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry. 3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Table 2. Absolute Maximum Ratings Parameter Symbol Power Supply VDD Storage Temperature Tstorage Clock and Data Input Range CLKIN, DATAINMechanical Shock Mechanical Vibration Solderability Gross and Fine Leak Resistance to Solvents
MIL-STD-883, Method 2002 MIL-STD-883, Method 2007 MIL-STD-883, Method 2003 MIL-STD-883, Method 1014, 100% Tested MIL-STD-883, Method 2016
Although ESD protection circuitry has been designed into the CD-700, proper precautions should be taken when handling and mounting. VI employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model.Human Body Model Charged Device Model 1000 V
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