The is a two-stage wide band monolithic low noise amplifier. The circuit is manufactured with a standard HEMT process : 0.25�m gate length, via holes through the substrate, air bridges and electron beam gate lithography. It is supplied in chip form. IN
Broad band performance 36-40GHz 2.5dB noise figure, 36-40GHz 15dB gain, � 0.5dB gain flatness Low DC power consumption, 20dBm 3rd order intercept point Chip size x 0.1mm
Tamb = +25�C Symbol Fop G P1dB Parameter Operating frequency range Noise figure, 36-40GHz Gain Output power at 1dB gain compression 12 Min Typ Max 40 3 Unit GHz dB dBmESD Protections : Electrostatic discharge sensitive device observe handling precautions !
Ref. -28-Aug.-02 1/8 Specifications subject to change without notice
Tamb = +25�C, Bias Conditions:Vd = +4V Symbol Fop G NF VSWRin VSWRout P1dB Vd
Parameter Operating frequency range Gain (1) Gain flatness (1) Noise figure (1) Input VSWR (1) Ouput VSWR (1) 3rd order intercept point Output power at 1dB gain compression DC Voltage Vd Vg(1) These values are representative of on-wafer measurements that are made without bonding wires
at the RF ports.When the chip is attached with typical 0.15nH input and output bonding wires, the indicated parameters should be improved. mA is the typical bias current used for on wafer measurements, with Vg1= Vg2. For optimum noise figure, the bias current could be reduced down to 30 mA, adjusting the Vg1,2 voltage.
Tamb = +25�C Symbol Vd Vg Vdg Pin Top Tsg Parameter Drain bias voltage Gate bias voltage Maximum drain to gate voltage (Vd-Vg) Maximum peak input power overdrive (2) Maximum continuous input power Operating temperature range Storage temperature range Values to +125 Unit V dBm �C
(1) Operation of this device above anyone of these paramaters may cause permanent damage. (2) Duration < 1s.Ref. -28-Aug.-02 2/8 Specifications subject to change without notice