CLC-CAPT-PCASM Data Capture Board User's Guide
The CLC3790093 Data Capture Board enables simple evaluation of National Semiconductor's High Speed Analog to Digital Converters (ADCs) and the Diversity Receiver Chip Set (DRCS). The Data Capture Board interfaces the outputs of these devices to the standard serial port available on the back of most Personal Computers (PCs). We have provided PC software to control the data capture function and Matlab� scripts for data analysis. A block diagram of the evaluation test bed is shown below. The Data Capture Board contains a field-programmable gate array (FPGA) that controls its operation. An EPROM configures the FPGA after power is applied. The serial interface is provided by a UART (Universal Asynchronous Receiver/Transmitter), an oscillator, and a level translator IC. The captured data is stored in either three x 8 static RAMs (organized into 24-bit words) in a FIFO containing 32K 18-bit words. LEDs provide a visual indication of activity. DIP switches and a jumper configure several capture functions.
I. Introduction II. Capturing Data from ADC Evaluation Boards III. Capturing Data from the DRCS Evaluation Boards IV. Data Analysis using Matlab Script FilesSection II. Capturing Data from ADC Evaluation Boards
Getting Started To use the Data Capture board to capture data from a National Semiconductor Analog to Digital converter, you will need the following hardware, software, and documentation.National Semiconductor High-Speed Converter Evaluation Test Bed
FILTERED SIGNAL SOURCE OPTIONAL CLOCK SOURCE
(Mineola, NY) passive filters are used for most of our converter testing. 8. Clock Source. If you wish to test the ADC with a fixed clock frequency, you may install a standard TTL oscillator in the socket provided on the evaluation board. Otherwise, you will need to provide a low phase noise sinewave or square wave clock source at the appropriate SMA connector on the evaluation board. An amplitude 16dBm is recommended. Here, again, the is a good choice.
1. CLC3790093 Data Capture Board (CLC-CAPT-PCASM) 2. CLCXXXX Evaluation Board. Several ADC products can be evaluated with this system. Each product has a unique evaluation board which plugs into the data capture board. In order to determine the compatibility of specific ADC evaluation boards to the data capture board, please refer to the "Basestation A/D Converter Evaluation Board Interoperability Guide" available on our website at http://www.national.com/ appinfo/wbp. 3. Personal Computer. An IBM-Compatible PC running Windows� 95, Windows� 98, or Windows� NT. The PC should have an available serial port capable of operating at 115,200 baud. These ports are usually labeled and referred as COM1 and COM2. The captured data is stored in a file on the PC to allow custom analysis. 4. Serial Cable. A standard serial interface cable is provided. This cable connects the data capture board to the PC. 5. Power Supply. The data capture board requires a single +5V supply. This power is applied at connector A 2-amp supply will provide enough current for the evaluation board and the data capture board. Note that the power for the evaluation board is provided from the data capture board through the 64-pin connector J1. 6. Input signal. You can provide any type of input signal that you feel is appropriate to your system testing. The data analysis software provided with the data capture board is oriented toward analysis of single tone sinewave inputs. Our recommendation for high purity, low phase noise reference signal sources is the Hewlett Packard HP8644B synthesizer. It provides an excellent input stimulus for evaluating ADC performance. 7. Bandpass or lowpass filter. Even with a good sinewave source, you will need to filter out the harmonics of the signal source. A bandpass filter also enables filtering of the wideband noise of the reference source. As an example, Allen Avionics
1. National Semiconductor Software. All of the required software is provided on a CD-ROM. To install the software now, insert the CD-ROM into your computer and follow the directions. The default installation copies all of the files to a directory called "c:\nsc". The data capture software is called "capture.exe". 2. Matlab. A copy of Matlab version 5.1 or later is required to operate the analysis routines. If you simply wish to capture data to a file on your PC and process the data with your own analysis software, then you will not need Matlab. For more information about Matlab, please see their website at http://www.mathworks.com. 3. Matlab script files. The Matlab script files for data analysis are located in the "c:\nsc\mfiles" directory. These script files are run from the Matlab command prompt.
Applicable product data sheets and user guides can be found on the provided CD-ROM, with the most current versions available on our website at: http://www.national.com/appinfo/wbp If you are evaluating the Diversity Receiver Chip Set, please refer to Section III of this manual. Operation of Data Capture Board When evaluating the performance of an ADC, the data capture board has two main modes of operation. In the first mode, data is captured from the evaluation board under test at the full sample rate of the ADC. A contiguous set of 32k data samples is captured into a FIFO memory on the board, and then this data is moved over to the at a slower rate. The data set is stored in a file on the hard drive for later analysis. The data is stored in an ASCII file in exactly the format that it is output from the converter. For the CLC5957, the two's complement 12-Bit data is stored as numbers ranging from 4095. In the case of the 14-bit CLC5958, the two's complement data ranges from to 16383. Each value is terminated with a carriage return, hexadecimal 0D. Note that the two's complement number can be converted to offset binary by inverting the MSB. This is the first step in the Matlab routine for FFT analysis.
CLC5956 Data Analog Input Ain- Ain Ain- > Ain > AinAin AinCLC5958 Data Analog Input Ain- Ain Ain- > Ain > AinAin Ain-
Condition - Full Scale - Mid Scale + Mid Scale + Full Scale Condition - Full Scale - Mid Scale + Mid Scale + Full Scale
In the second mode of operation, the "Histogram" mode, the data capture board operates as a hardware histogrammer. The board does not collect a contiguous record from the ADC; instead, it compiles statistical information by counting the number of times that the ADC outputs each code. The most significant 15 bits of the converter define 32K histogram bins. The MSB of the data is inverted before being stored (all data is treated as offset binary format). ADC data is aligned to the least significant bit, and unused higher bits are set to 0s. Each bin is cleared initially. The ADC output code is used as the address for the SRAM on the board, and as each code is read by the Data Capture board, the data at that location in the SRAM is read, incremented and written back to the SRAM. This counting requires multiple clock cycles, so the data is not counted in real time. In fact, 11 samples of data are missed for each sample that is counted. The histogram capture terminates when a bin reaches the count specified by DIP switches 4 and 5. The 32K histogram bin counts are then returned via the serial port. If the input signal to the ADC is a pure sinusoid, then the histogram information can be compared to the theoretical probability density of a sinusoid and the linearity of the ADC can be calculated. The supplied Matlab script DNL_INL uses this method. Please refer to the IEEE Standard for Digitizing Waveform Recorders (IEEE Std 1057-1994) for more information about this technique. Hardware ConfigurationFPGA Performs: State Machine Signal Format Conversion Data Routing
Note: Primary data path shown. Control lines not shown
Five of the eight DIP switches are used to configure several capture functions as follows. DIP switch 1: This DIP switch specifies whether a Diversity Receiver Evaluation Board or an ADC Evaluation Board is attached to the Data Capture Board. ON ADC Evaluation Board is attached. Captured data is aligned to the least significant bit with unused higher bits set to 0s. DIP switches 2 and 3: When DIP switch ON to indicate that an ADC Evaluation Board is attached, DIP switches 2 and 3 specify the width of the ADC data so it can be aligned to the least significant bit and unused higher bits can be set to 0s.
The data capture board has 2 jumpers that must be configured before use. The first jumper, WCLK, selects the clock source for the FIFO. When capturing data from an ADC evaluation board, WCLK should be set to RDY2. This selects the DR (Data Ready) clock line from the ADC evaluation board pin 20B. The second jumper, VCCD, sets the supply voltage for the ADC output buffers. Unless the ADC evaluation board instructions specify otherwise, this jumper should be set to +5.
DIP switches 4 and 5: These DIP switches specify the maximum histogram bin count. The histogram capture terminates when any bin reaches the count specified by these switches.
A maximum count of 16384 corresponds to approximately 2.5 million total samples for a 12-Bit ADC. The capture is very fast (on the order of 1 second for a 52 MSPS clock rate) so there is not much advantage in setting the switches for a lower maximum count. The other settings are more useful for the DRCS evaluations because the effective clock rate can become very low with certain output formats and decimation ratios. 3