DAC1210LCJ-1 Datasheet

12-bit, Compatible, Double-buffered D to a Converters


Features, Applications

The DAC1208 and the DAC1230 series are 12-bit multiplying to A converters designed to interface directly with a wide variety of microprocessors 8085 Z-80 etc ) Double buffering input registers and associated control lines allow these DACs to appear as a two-byte ``stack'' in the system's memory I O space with no additional interfacing logic required The DAC1208 series provides all 12 input lines to allow single buffering for maximum throughput when used with 16-bit processors These input lines can also be externally configured to permit an 8-bit data interface The DAC1230 series can be used with an 8-bit data bus directly as it internally formulates the 12-bit DAC data from its 8 input lines All of these DACs accept left-justified data from the processor The analog section is a precision silicon-chromium (Si-Cr) R-2R ladder network and twelve CMOS current switches An inverted R-2R ladder structure is used with the binary weighted currents switched between the IOUT1 and IOUT2 maintaining a constant current in each ladder leg independent of the switch state Special circuitry provides TTL logic input voltage level compatibility The DAC1208 series and DAC1230 series are the 12-bit members of a family of microprocessor compatible DACs (MICRO-DACsTM ) For applications requiring other resolutions the DAC1000 series for 10-bit and DAC0830 series for 8-bit are available alternatives


Linearity specified with zero and full-scale adjust only Direct interface to all popular microprocessors Double-buffered single-buffered or flow through digital data inputs Logic inputs which meet TTL voltage level specs (1 4V logic threshold) Works with g 10V reference full 4-quadrant multiplication Operates stand-alone (without mP) if desired All parts guaranteed 12-bit monotonic DAC1230 series is pin compatible with the DAC0830 series 8-bit MICRO-DACs

Current Settling Time Resolution Linearity (Guaranteed over temperature) Gain Tempco Low Power Dissipation Single Power Supply

TRI-STATE is a registered trademark of National Semiconductor Corp MICRO-DACTM is a trademark of National Semiconductor Corp C1995 National Semiconductor Corporation

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications (Notes 1 and 2) Supply Voltage (VCC) Voltage at Any Digital Input Voltage at VREF Input Storage Temperature Range Package Dissipation 25 C (Note 3) DC Voltage Applied or IOUT2 (Note 4) ESD Susceptability 17 VDC VCC to GND

Lead Temperature (Soldering 10 sec 300 C Temperature Range TMIN TA s TMAX 70 C Range of VCC 4 75 VDC to 16 VDC VCC to GND Voltage at Any Digital Input

VREF 10 000 VDC VCC 11 4 VDC 15 75 VDC unless otherwise noted Boldface limits apply from TMIN to TMAX (see Note 13) all other limits 25 C Parameter Resolution Linearity Error (End Point Linearity) Zero and Full-Scale Adjusted DAC1210 DAC1232 Zero and Full-Scale Adjusted DAC1210 DAC1232 Using Internal RFb Vref 7 13

Monotonicity Gain Error (Min) Gain Error (Max) Gain Error Tempco Power Supply Rejection Reference Input Resistance (Min) Reference Input Resistance (Max) Output Feedthrough Error VREF e 20 Vp-p e 100 kHz All Data Inputs Latched Low Output Capacitance All Data Inputs Latched High All Data Inputs Latched Low IOUT1 IOUT2 All Digital Inputs Latched High

Supply Current Drain Output Leakage Current IOUT1 IOUT2 Digital Input Threshold Digital Input Currents All Data Inputs Latched Low All Data Inputs Latched High Low Threshold High Threshold Digital Inputs k0 8V Digital Inputs l2 2V

Electrical Characteristics (Continued) VREF 10 000 VDC VCC 11 4 VDC 15 75 VDC unless otherwise noted Boldface limits apply from TMIN to TMAX (see Note 13) all other limits 25 C

Symbol Parameter Conditions See Note Typ (Note 10) Tested Limit (Note 5) Design Limit (Note 6) Units

AC CHARACTERISTICS ts tW tDS tDH tCS tCH Current Setting Time Write and XFER Pulse Width Min Data Setup Time Min Data Hold Time Min Control Setup Time Min Control Hold Time Min VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH ns ms

Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking Note 4 Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier The linearity error is degraded by approximately VOS d VREF For example if VREF e 10V then 1 mV offset VOS or IOUT2 will introduce an additional 0 01% linearity error Note 5 Tested and guaranteed to National's AOQL (Average Outgoing Quality Level) Note 6 Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels Guaranteed for VCC 15 75V and VREF a 10V Note 7 The unit FSR stands for full-scale range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular VREF value to indicate the true performance of the part The Linearity Error specification of the 012% of FSR(max) This guarantees that after performing a zero and full-scale adjustment the plot of the 4096 analog voltage outputs will each be within 012% c VREF of a straight line which passes through zero and full-scale The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs of very small percentage values typical of higher accuracy converters In this instance 1 ppm of FSR e VREF 106 is the conversion factor to provide an actual output voltage quantity For example the gain error tempco spec g 6 ppm FS C represents a worst-case full-scale gain error change with temperature from 75 (10b3) VREF which 075% of VREF Note 8 This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) ns A typical part will operate with tW of only 100 ns The entire write pulse must occur within the valid data interval for the specified tW tDS tDH and tS to apply Note 9 To achieve this low feedthrough in the D package the user must ground the metal lid If the lid is left floating the feedthrough is typically 6 mV Note 10 Typicals are 25 C and represent the most likely parametric norm Note 10 nA leakage current with RFb e 20k and VREF e 10V corresponds to a zero error of FS Note 12 Human body model 100 pF discharged through 5 kX resistor Note 13 Tested limit for b 1 suffix parts applies only 25 C



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