FEATURES Two Matched 12-Bit DACs on One Chip Direct Parallel Load of All 12 Bits for High Data Throughput Double-Buffered Digital Inputs 12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature +15 V Single Supply Operation DACs Matched to 1% Max Four-Quadrant Multiplication Improved ESD Resistance Packaged in a Narrow 0.3" 24-Lead DIP and 0.3" 24- Lead SOL Package Available in Die Form APPLICATIONS Automatic Test Equipment Robotics/Process Control/Automation Digital Gain/Attenuation Control Ideal for Battery-Operated Equipment
The is a dual 12-bit, double-buffered, CMOS digitalto-analog converter. It has a 12-bit wide data port that allows a 12-bit word to be loaded directly. This achieves faster throughput time in stand-alone systems or when interfacing a 16-bit processor. A common 12-bit input TTL/CMOS compatible data port is used to load the 12-bit word into either of the two DACs. This port, whose data loading is similar to that of a RAM's write cycle, interfaces directly with most 12-bit and 16-bit bus systems. (See DAC8248 for a complete 8-bit data bus interface product.) A common bus allows the to be packaged in a narrow 24-lead 0.3" DIP and save PCB space. The DAC is controlled with two signals, WR and LDAC. With logic low at these inputs, the DAC registers become transparent. This allows direct unbuffered data to flow directly to either DAC output selected by DAC A/DAC B. Also, the DAC's
double-buffered digital inputs will allow both DACs to be simultaneously updated. DAC8222's monolithic construction offers excellent DAC-toDAC matching and tracking over the full operating temperature range. The chip consists of two thin-film R-2R resistor ladder networks, four 12-bit registers, and DAC control logic circuitry. The device has separate reference-input and feedback resistors for each DAC and operates on a single supply from +15 V. Maximum power dissipation +5 V using zero or VDD logic levels is less than 0.5 mW. The DAC8222 is manufactured with highly stable thin-film resistors on an advanced oxide-isolated, silicon-gate, CMOS technology. Improved latch-up resistant design eliminates the need for external protective Schottky diodes.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 � Analog Devices, Inc., 2000
VDD +15 V, VREF A = VREF +10 V, VOUT A = VOUT 0 V; AGND = DGND TA = Full Temperature Range Specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)
Parameter STATIC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Gain Error1 Gain Temperature Coefficient Gain/Temperature Output Leakage Current IOUT A (Pin 2), IOUT B (Pin 24) Input Resistance (VREF A, VREF B) Input Resistance Match DIGITAL INPUTS Digital Input High Digital Input Low Input Current Input Capacitance2 POWER SUPPLY Supply Current DC Power Supply Rejection Ratio (Gain/VDD) Symbol Conditions N INL DNL GFSE Min DAC8222A/E/G DAC8222F/H All Grades are Guaranteed Monotonic DAC8222G DAC8222F/H (Notes 2, 7) All Digital Inputs (Note TA = Full Temp. Range Endpoint Linearity Error Typ Max Units Bits LSB ppm/�C k %
VDD +5 V VDD +15 V VDD +5 V VDD +15 V VIN V or VDD TA = Full Temp. Range and VINL or VINH DB0�DB11 WR, LDAC, DAC A/DAC B All Digital Inputs VINL or VINH All Digital Inputs V or VDD � 5%
AC PERFORMANCE CHARACTERISTICS2 Propagation Delay4, 5 tPD = +25�C Current Settling Time5, 6 Digital Inputs = All 0s Output Capacitance CO COUT A, COUT B Digital Inputs = All 1s COUT A, COUT B VREF A to IOUT A; VREF 20 V p-p; AC Feedthrough at FTA = 100 kHz; = +25�C IOUT A or IOUT B VREF B to IOUT B; VREF 20 V p-p; FTB = 100 kHz; = +25�C SWITCHING CHARACTERISTICS2, 3 DAC Select to Write Set-Up Time DAC Select to Write Hold Time LDAC to Write Set-Up Time LDAC to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width LDAC Pulse Width tAS tAH tLS tLH tDS tDH tWR tLWD +25�C
NOTES 11 Measured using internal RFB A and RFB B. Both DAC digital inputs Guaranteed and not tested. 13 See timing diagram. 14 From 50% of digital input 90% of final analog output current. VREF A = VREF +10 V; OUT A, OUT B load 100 , CEXT = 13 pF. 15 WR, LDAC V to VDD or VDD 0 V.
Settling time is measured from 50% of the digital input change to where the output voltage settles within 1/2 LSB of full scale. Gain TC is measured from �C to TMIN or from +25�C to TMAX. 18 These limits apply for the commercial and industrial grade products. 19 Absolute temperature coefficient is approximately +50 ppm/ �C. 10 These limits also apply as typical values for +12 V with +5 V CMOS logic levels and = +25�C. Specifications subject to change without notice.
VDD to AGND. +17 V VDD to DGND. +17 V AGND to DGND. �0.3 V, VDD +0.3 V Digital Input Voltage to DGND. �0.3 V, VDD +0.3 V IOUTA, IOUTB to AGND. �0.3 V, VDD +0.3 V VREFA, VREFB to AGND. 25 V VRFBA, VRFBB to AGND. 25 V Operating Temperature Range AW Version. to +125�C EW, FW, FP Versions. to +85�C GP, HP, HS Versions. to +70�C Junction Temperature. +150�C Storage Temperature. to +150�C Lead Temperature (Soldering, 60 sec). +300�C Package Type 24-Lead Hermetic DIP (W) 24-Lead Plastic DIP (P) 24-Lead SOL (S) 32 24 Units �C/W
NOTE JA is specified for worst-case mounting conditions, i.e., qJA is specified for device in socket for Cerdip, and P-DIP packages; JA is specified for device soldered to printed circuit board for SO package.
1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFB. 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Do not insert this device into powered sockets; remove power before insertion or removal. 4. Use proper antistatic handling procedures. 5. Devices can suffer permanent damage and/or reliability degradation if stressed above the limits listed under Absolute Maximum Ratings for extended periods.
ORDERING GUIDE Model DAC8222FP DAC8222FS INL GFSE (LSB) Temperature Range to +85�C Package Description P-DIP-24 SOL-24 Package Option N-24 R-24
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8222 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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