HomedatasheetDDU66C-125MD4

DDU66C-125MD4 Datasheet

5-tap, Hcmos-interfaced Fixed Delay Line
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Description

Features, Applications

FEATURES

Five equally spaced outputs Fits standard 14-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered T L fan-out capability

The DDU66C-series device a 5-tap digitally buffered delay line. The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time an T1-T5 Tap Outputs amount given by the device dash number. For dash numbers less than 40, VDD +5 Volts the total delay of the line is measured from to T5, with the nominal value GND Ground given by the dash number. The nominal tap-to-tap delay increment is given 1/4 of this number. The inherent delay from T1 is nominally 8.0ns. For dash numbers greater than or equal to 40, the total delay of the line is measured from to T5, with the nominal value given by the dash number. The nominal tap-to-tap delay increment is given 1/5 of this number.

Minimum input pulse width: 40% of total delay Output rise time: 8ns typical Supply voltage: � 5% Supply current: ICCL = 40�a typical ICCH = 10ma typical Operating temperature: 70� C Temp. coefficient of total delay: 300 PPM/�C

* Total delay is referenced to first tap output Input to first tap � 2ns NOTE: Any dash number between 10 and 250 not shown is also available.

The DDU66C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small 40% of the total delay and periods as small 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.

The DDU66C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used.

PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VDD VIN TSTRG TLEAD MIN -0.3 -55 MAX 150 300 UNITS NOTES

to 5.25V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Current SYMBOL VOH VOL IOH IOL VIH VIL IIH MIN 3.98 TYP 4.4 0.15 MAX UNITS V �A NOTES VDD = 5.0, IOH = MAX VIH = MIN, VIL = MAX VDD = 5.0, IOL = MAX VIH = MIN, VIL = MAX




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