DDU8C3-5030A1 Datasheet

Fixed 5-tap Lvcmos Delay Line


Features, Applications


Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered T L fan-out capability

The DDU8C3-series device a 5-tap digitally buffered delay line. The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time an T1-T5 Tap Outputs amount determined by the device dash number (See Table). For dash VDD +3.3 Volts numbers 5020 and above, the total delay of the line is measured from IN to GND Ground T5, and the nominal tap-to-tap delay increment is given by one-fifth of the total delay. For dash numbers below 5020, the total delay is measured from to T5, and the delay increment is given by one-fourth of the total delay.

Minimum input pulse width: 40% of total delay Output rise time: 2ns typical Supply voltage: � 0.3V Supply current: ICCL = 40�a typical ICCH = 7ma typical Operating temperature: 85� C Temp. coefficient of total delay: 300 PPM/�C

* Total delay is referenced to first tap output Input to first tap � 1ns NOTE: Any dash number between 5004 and 5250 not shown is also available. � 2000 Data Delay Devices

The DDU8C3 tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small 40% of the total delay and periods as small 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.

The DDU8C3 relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used.

PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VDD VIN TSTRG TLEAD MIN -0.3 -55 MAX 150 300 UNITS NOTES

to 3.60V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Current SYMBOL VOH VOL IOH IOL VIH VIL IIH MIN 3.00 TYP 3.20 0.10 MAX UNITS V �A NOTES VDD = 3.3, IOH = MAX VIH = MIN, VIL = MAX VDD = 3.3, IOL = MAX VIH = MIN, VIL = MAX



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