HomedatasheetEPM7064SLC84-7

EPM7064SLC84-7 Datasheet

CPLD - Complex Programmable Logic Devices
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Description

The EPM7064SLC84-7 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064SLC84-7 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as EPM7064SLC84-7and devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. EPM7064SLC84-7 Features • High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture• 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532• Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices• Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells• Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates • 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)• PCI-compliant devices available
Features

Parameters

[{"Name":" Supply Voltage - Min:","Value":"3 V"},{"Name":" Supply Voltage - Max:","Value":"3.6 V"},{"Name":"Minimum Operating Temperature:","Value":"0 C"},{"Name":"Number of Gates:","Value":"1250"},{"Name":"Maximum Operating Temperature:","Value":"+ 70 C"},{"Name":"Operating Supply Voltage:","Value":"5 V"},{"Name":"Delay Time:","Value":"5 ns"},{"Name":"Maximum Operating Frequency:","Value":"175.4 MHz"},{"Name":"Number of Macrocells:","Value":"64"},{"Name":"","Value":""}]

Manufacturer information

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