M5LV-512/184-12HI Datasheet

7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)


◆ High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os

◆ Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package

◆ Performance features to fit system needs
— 5.5 ns tPDCommercial, 7.5 ns tPDIndustrial
— 182 MHz fCNT
— Four programmable power/speed settings per block

◆ Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms



Manufacturer information


Lattice Semiconductor, founded in 1983 and headquartered in Portland, Oregon, is the global leader in smart connectivity solutions. They provide market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products. The Company's broad end-market exposure extends from consumer electronics to industrial equipment, communications infrastructure and licensing

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