TA80960CA-16 Datasheet



This document provides electrical characteristics for the 25 and 16 MHz versions of the 80960CA. For a detailed description of any 80960CA functional topic—other than parametric performance—consult the 80960CA Product Overview (Order No. 270669) or the i960É CA Microprocessor User’s Manual (Order No. 270710). To obtain data sheet updates and errata, please call Intel’s FaxBACKÉ data-on-demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel’s technical BBS (916-356-3600).

The 80960CA is the second-generation member of the 80960 family of embedded processors. The 80960CA is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64-bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two in structions every clock and peak at execution of three instructions per clock.
A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s high speed external memory sub-system. In addition, the 80960CA’s on-chip caching of instructions, procedure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system’s slower, cost sensitive, main memory subsystem.

■ 32-bit Parallel Architecture
   — Two Instructions/clock Execution
   — Load/Store Architecture
   — Sixteen 32-bit Global Registers
   — Sixteen 32-bit Local Registers
   — Manipulates 64-bit Bit Fields
   — 11 Addressing Modes
   — Full Parallel Fault Model
   — Supervisor Protection Model
■ Fast Procedure Call/Return Model
   — Full Procedure Call in 4 Clocks
■ On-Chip Register Cache
   — Caches Registers on Call/Ret
   — Minimum of 6 Frames Provided
   — Up to 15 Programmable Frames
■ On-Chip instruction Cache
   — 1 Kbyte Two-Way Set Associative
   — 128-bit Path to instruction Sequencer
   — Cache-Lock Modes
   — Cache-Off Mode
■ High Bandwidth On-Chip Data RAM
   — 1 Kbyte On-Chip Data RAM
   — Sustains 128 bits per Clock Access
■ Four On-Chip DMA Channels
   — 59 Mbytes/s Fly-by Transfers
   — 32 Mbytes/s Two-Cycle Transfers
   — Data Chaining
   — Data Packing/Unpacking
   — Programmable Priority Method
■ 32-Bit Demultiplexed Burst Bus
   — 128-bit internal Data Paths to and from Registers
   — Burst Bus for DRAM Interfacing
   — Address Pipelining Option
   — Fully Programmable Wait States
   — Supports 8-, 16- or 32-bit Bus Widths
   — Supports Unaligned Accesses
   — Supervisor Protection Pin
■ Selectable Big or Little Endian Byte Ordering
■ High-Speed Interrupt Controller
   — Up to 248 External interrupts
   — 32 Fully Programmable Priorities
   — Multi-mode 8-bit Interrupt Port
   — Four internal DMA Interrupts
   — Separate, Non-maskable interrupt Pin
   — Context Switch in 750 ns Typical
■ Product Grades Available
   — SE3: -40°C to +110°C




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Intel and Altera announced on June 1, 2015, that they had entered into a definitive agreement under which Intel would acquire Altera. The transaction closed December 28, 2015. The acquisition couples Intel’s leading-edge products and manufacturing process with Altera’s leading field-programmable gate array (FPGA) technology. The combination enables new classes of products that meet customer needs in the data center and Internet of Things (IoT) market segments.

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