HomedatasheetCA3046M96

CA3046M96 Datasheet

General Purpose
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Description

Features, Applications

The CA3046 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially connected pair. The transistors of the CA3046 are well suited to a wide variety of applications in low power systems in the DC through VHF range. They may be used as discrete transistors in conventional circuits. However, in addition, they provide the very significant inherent integrated circuit advantages of close electrical and thermal matching.

Features

Two Matched Transistors - VBE Match. �5mV - IIO Match.2�A (Max) Low Noise Figure. 3.2dB (Typ) 1kHz 5 General Purpose Monolithic Transistors Operation From to 120MHz Wide Operating Current Range Full Military Temperature Range

PART NUMBER (BRAND) CA3046M96 (3046) TEMP. RANGE ( oC) to 125 PACKAGE 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC Tape and Reel PKG. NO. E14.3 M14.15

Applications

Three Isolated Transistors and One Differentially Connected Transistor Pair for Low Power Applications at Frequencies from DC Through the VHF Range Custom Designed Differential Amplifiers Temperature Compensated Amplifiers See Application Note, AN5296 "Application of the CA3018 Integrated-Circuit Transistor Array" for Suggested Applications

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright � Intersil Americas Inc. 2001

Collector-to-Emitter Voltage (VCEO). 15V Collector-to-Base Voltage (V CBO). 20V Collector-to-Substrate Voltage (VCIO, Note 1). 20V Emitter-to-Base Voltage (VEBO). 5V Collector Current (IC). 50mA

Thermal Resistance (Typical, Note JA ( oC/W) JC (oC/W) PDIP Package. 180 N/A SOIC Package. 220 N/A Maximum Power Dissipation (Any One Transistor). 300mW Maximum Junction Temperature (Plastic Package). 150oC Maximum Storage Temperature Range. to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES: 1. The collector of each transistor of the CA3046 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. JA is measured with the component mounted on an evaluation PC board in free air.

= 25oC, characteristics apply for each transistor CA3046 as specified SYMBOL TEST CONDITIONS = 10�A, ICI = 0 VCB = 0 VCE = 0 VCE = 10�A VCE = 1mA VBE VCE = 10mA MIN TYP MAX UNITS

Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage Collector Cutoff Current (Figure 1) Collector Cutoff Current (Figure 2) Forward Current Transfer Ratio (Static Beta) (Note 3) (Figure 3)

V(BR)CBO V(BR)CEO V(BR)CIO V(BR)EBO ICBO ICEO hFE

Input Offset Current for Matched Pair Q1 and - IIO2| (Note 3) (Figure 4) Base-to-Emitter Voltage (Note 3) (Figure 5)

Magnitude of Input Offet Voltage for Differential Pair - VBE2| (Note 3) (Figures 5, 7) Magnitude of Input Offset Voltage for Isolated Transistors - VBE3| (Note 3) (Figures 5, 7) Temperature Coefficient of Base-to-Emitter Voltage (Figure 6) Collector-to-Emitter Saturation Voltage Temperature Coefficient: Magnitude of Input Offset Voltage (Figure 7) DYNAMIC CHARACTERISTICS Low Frequency Noise Figure (Figure 9) Low Frequency, Small Signal Equivalent Circuit Characteristics Forward Current Transfer Ratio (Figure 11) Short Circuit Input Impedance (Figure 11) Open Circuit Output Impedance (Figure 11) hFE hIE hOE V BE -------------T VCES V IO ---------------T

PARAMETER Open Circuit Reverse Voltage Transfer Ratio (Figure 11) Admittance Characteristics Forward Transfer Admittance (Figure 12) Input Admittance (Figure 13) Output Admittance (Figure 14) Reverse Transfer Admittance (Figure 15) Gain Bandwidth Product (Figure 16) Emitter-to-Base Capacitance Collector-to-Base Capacitance Collector-to-Substrate Capacitance NOTE: 3. Actual forcing current is via the emitter for this test. YFE YIE YOE YRE fT CEB CCB CCI = 1kHz, VCE = 1kHz, VCE = 1kHz, VCE = 1kHz, VCE = 1mA VCE = 3mA VEB = 0 VCB = 0 VCS + j0.03 See Fig. MHz = 25oC, characteristics apply for each transistor CA3046 as specified (Continued) SYMBOL hRE TEST CONDITIONS = 1kHz, VCE = 1mA MIN TYP x 10-4 MAX UNITS -

FIGURE 1. TYPICAL COLLECTOR-TO-BASE CUTOFFCURRENT vs TEMPERATURE FOR EACH TRANSISTOR
120 VCE = 3V STATIC FORWARD CURRENT TRANSFER RATIO (hFE) 25 oC hFE 1.0 BETA RATIO 1.1
FIGURE 2. TYPICAL COLLECTOR-TO-EMITTER CUTOFF CURRENT vs TEMPERATURE FOR EACH TRANSISTOR

FIGURE 3. TYPICAL STATIC FORWARD CURRENT TRANSFER RATIO AND BETA RATIO FOR Q1 AND Q2 vs EMITTER CURRENT

FIGURE 4. TYPICAL INPUT OFFSET CURRENT FOR MATCHED TRANSISTOR PAIR Q1Q2 vs COLLECTOR CURRENT

Features

Parameters

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