The CA3086 consists of five general-purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially connected pair. The transistors of the CA3086 are well suited to a wide variety of applications in low-power systems at frequencies from to 120MHz. They may be used as discrete transistors in conventional circuits. However, they also provide the very significant inherent advantages unique to integrated circuits, such as compactness, ease of physical handling and thermal matchingApplications
Three Isolated Transistors and One Differentially Connected Transistor Pair For Low-Power Applications from to 120MHz General-Purpose Use in Signal Processing Systems Operating in the to 190MHz Range Temperature Compensated Amplifiers See Application Note, AN5296 "Application of the CA3018 Integrated-Circuit Transistor Array" for Suggested Applications
PART NUMBER (BRAND) CA3086M96 (3086) TEMP. RANGE ( oC) to 125 PACKAGE 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC Tape and Reel PKG. NO. E14.3 M14.15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright � Intersil Americas Inc. 2001
The following ratings apply for each transistor in the device: Collector-to-Emitter Voltage, V CEO. 15V Collector-to-Base Voltage, VCBO. 20V Collector-to-Substrate Voltage, VCIO (Note 1). 20V Emitter-to-Base Voltage, VEBO. 5V Collector Current, IC. 50mA
Thermal Resistance (Typical, Note JA ( oC/W) JC (oC/W) PDIP Package. 180 N/A SOIC Package. 220 N/A Maximum Power Dissipation (Any one transistor). 300mW Maximum Junction Temperature (Plastic Package). 150oC Maximum Storage Temperature Range. to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The collector of each transistor in the CA3086 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid undesirable coupling between transistors, the substrate (Terminal 13) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. JA is measured with the component mounted on an evaluation PC board in free air.
= 25oC, For Equipment Design SYMBOL V(BR)CBO V(BR)CEO V(BR)ClO V(BR)EBO ICBO ICEO hFE TEST CONDITIONS = 10�A, ICI = 0 VCB = 0, VCE = 0, VCE = 1mA MIN TYP (Figure 2) 100 MAX 100 5 UNITS nA �A
Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Collector-to-Substrate Breakdown Voltage Emitter-to-Base Breakdown Voltage Collector-Cutoff Current (Figure 1) Collector-Cutoff Current (Figure 2) DC Forward-Current Transfer Ratio (Figure 3)= 25oC, Typical Values Intended Only for Design Guidance TYPICAL VALUES V mV/oC V
DC Forward-Current Transfer Ratio (Figure 3) Base-to-Emitter Voltage (Figure 4)
VBE Temperature Coefficient (Figure 5) Collector-to-Emitter Saturation Voltage Noise Figure (Low Frequency)
PARAMETER Low-Frequency, Small-Signal EquivalentCircuit Characteristics: Forward Current-Transfer Ratio (Figure 6) Short-Circuit Input Impedance (Figure 6) Open-Circuit Output Impedance (Figure 6) Open-Circuit Reverse-Voltage Transfer Ratio (Figure 6) Admittance Characteristics: Forward Transfer Admittance (Figure 7) Input Admittance (Figure 8) Output Admittance (Figure 9) Reverse Transfer Admittance (Figure 10) Gain-Bandwidth Product (Figure 11) Emitter-to-Base Capacitance Collector-to-Base Capacitance Collector-to-Substrate Capacitance yFE yIE yOE yRE fT CEBO CCBO CClO VCE = 3mA VEB = 0 VCB = 0 hFE hIE hOE hRE = 25oC, Typical Values Intended Only for Design Guidance (Continued) TYPICAL VALUES