HomedatasheetCA3096CM96

CA3096CM96 Datasheet

General Purpose
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Description

Features, Applications

Description

The CA3096C, CA3096, and CA3096A are general purpose high voltage silicon transistor arrays. Each array consists of five independent transistors (two PNP and three NPN types) on a common substrate, which has a separate connection. Independent connections for each transistor permit maximum flexibility in circuit design. Types CA3096A, CA3096, and CA3096C are identical, except that the CA3096A specifications include parameter matching and greater stringency in ICBO , ICEO , and VCE(SAT). The is a relaxed version of the CA3096.

Applications

Five-Independent Transistors - Three NPN and - Two PNP Differential Amplifiers DC Amplifiers Sense Amplifiers Level Shifters Timers Lamp and Relay Drivers Thyristor Firing Circuits Temperature Compensated Amplifiers Operational Amplifiers

PART NUMBER (BRAND) CA3096M96 (3096) TEMP. RANGE (oC) to 125 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel PKG. NO. E16.3 M16.15

ICEO (nA) (Max) NPN PNP VCE SAT (V) (Max) NPN |VIO| (mV) (Max) NPN PNP |IIO| (�A) (Max) NPN PNP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright � Intersil Corporation 1999

NPN Collector-to-Emitter Voltage, VCEO CA3096C. 24V Collector-to-Base Voltage, VCBO CA3096C. 30V Collector-to-Substrate Voltage, VCIO (Note CA3096C. 30V Emitter-to-Substrate Voltage, VEIO CA3096A. CA3096C. Emitter-to-Base Voltage, VEBO CA3096C. 6V Collector Current, IC (All Types). 50mA PNP -24V -10mA

Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package. 90 SOIC Package. 125 Maximum Power Dissipation (Each Transistor, Note 3). 200mW Maximum Junction Temperature (Plastic Package). 150oC Maximum Storage Temperature to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES: 1. The collector of each transistor of the CA3096 is isolated from the substrate by an integral diode. The substrate (Terminal 16) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. JA is measured with the component mounted on an evaluation PC board in free air. 3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal resistances to calculate the junction temperature.

PARAMETER ICEO V(BR)CEO V(BR)CBO V(BR)EBO V(BR)ElO VCE SAT VBE (Note 4) hFE (Note 4)

Emitter-to-Base Zener Voltage Collector-to-Emitter Saturation Voltage Base-to-Emitter Voltage DC Forward-Current Transfer Ratio

V(BR)CEO Collector-to-Emitter Breakdown Voltage V(BR)CBO Collector-to-Base Breakdown Voltage V(BR)CIO Collector-to-Substrate Breakdown Voltage

V(BR)EBO Emitter-to-Base Breakdown Voltage NOTE: 4. Actual forcing current is via the emitter for this test.

|VBE/T| Magnitude of Temperature Coefficient: (for each transistor)

FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage Absolute Input Offset Current Absolute Input Offset Voltage Temperature Coefficient |VIO| |IIO| V IO ----------------T VCE mV �A �V/oC

FOR TRANSISTORS Q4 AND Q5 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage Absolute Input Offset Current Absolute Input Offset Voltage Temperature Coefficient |VIO| |IIO| V IO ----------------T VCE mV nA �V/oC


Features

Parameters

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Manufacturer information

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