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CMOS/SOS Low Power with Video Speed (Typ). 25mW Parallel Conversion Technique Single Power Supply Voltage. 7.5V 25MHz Sampling Rate (40ns Conversion Time) at 5V Supply 4-Bit Latched Three-State Output with Overflow and Data Change Outputs 1/ LSB Maximum Nonlinearity (A Version) 8 Inherent Resistance to Latch-Up Due to SOS Process Bipolar Input Range with Optional Second Supply Wide Input Bandwidth (Typ). 25MHzDescription
The Intersil is a CMOS parallel (FLASH) analog-todigital converter designed for applications demanding both low-power consumption and high speed digitization. Digitizing at 25MHz, for example, requires only about 35mW. The CA3304 operates over a wide, full-scale signal input voltage range up to the supply voltage. Power consumption is as low as 10mW, depending upon the clock frequency selected. The intrinsic high conversion rate makes the CA3304 types ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3304s in series to increase the resolution of the conversion system. A series connection of two CA3304s may be used to produce 5-bit, 25MHz converter. Operation of two CA3304s in parallel doubles the conversion speed (i.e., increases the sampling rate from 50MHz). A data change pin indicates when the present output differs from the previous, thus allowing compaction of data storage. Sixteen paralleled auto-balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel-bit outputs in the CA3304. Fifteen comparators are required to quantize all input voltage levels in this 4-bit converter, and the additional comparator is required for the overflow bit.Applications
High Speed A/D Conversion Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research General-Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis Robot Vision RSSI Circuits
PART NUMBER LINEARITY (INL, DNL) CA3304AD �0.25 LSB �0.125 LSB �0.25 LSB �0.125 LSB �0.25 LSB �0.125 LSB SAMPLING RATE 25MHz (40ns) TEMP. RANGE (oC) to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC (W) 16 Ld SOIC (W) 16 Ld SBDIP 16 Ld SBDIP PKG. NO. M16.3 D16.3
BIT 1 (LSB) 1 BIT 2 BIT 3 BIT 4 DATA CHANGE (DC) 5 OVERFLOW (OF) CE2 7 VSS 8 16 VDD 15 CLK 14 VAA13 VREF 12 VREF + 11 VIN 10 VAA+ 9 CE1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright � Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
DC Supply Voltage Range (VDD or VAA+) (Voltage Referenced to VSS or VAA- Terminal, Whichever is More Negative). to +8V Input Voltage Range CE1, CE2 Inputs. VSS -0.5V to VDD +0.5V Clock, VREF+, VREF-, VIN Inputs. VAA- -0.5V to VAA- +0.5V DC Input Current, Any Input. � 20mA
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) SBDIP Package. 80 22 PDIP Package. 90 N/A SOIC Package. 100 N/A Maximum Junction Temperature Ceramic Package. 175oC Plastic Package. 150oC Maximum Storage Temperature Range (TSTG). to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)
Recommended Supply Voltage Range (VDD or VAA+). to 7.5V Recommended VAA+ Voltage Range. VDD -1V to VDD +2.5V Recommended VAA- Voltage Range. VSS -2.5V to VSS +1V Operating Temperature to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE: JA is measured with the component mounted on an evaluation PC board in free air.
= 25oC, VREF+ = 2V, VDD = VAA+ = 5V, VAA- = VREF - = VSS = GND, fCLK = 25MHz Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SYSTEM PERFORMANCE Resolution Input Errors Integral Linearity Error Differential Linearity Error Offset Error (Unadjusted) Gain Error (Unadjusted) CA3304A CA3304
DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Conversion Timing Aperture Delay = 25MHz, fIN = 25MHz, fIN = 25MHz, fIN = 25MHz, fIN = 25MHz, fIN = 25MHz, fIN = 5MHz Effective Number of Bits, ENOB = 25MHz, fIN = 25MHz, fIN = 5MHz ANALOG INPUTS Input Range Input Loading Full Scale Input Range Input Capacitance Input Current VIN = 2V (Note 2) (Notes VAA ns dB dBc Bits
Signal to Noise Ratio, SNR RMS Signal = RMS Noise Signal to Noise Ratio, SINAD RMS Signal = RMS Noise + Distortion Total Harmonic Distortion, THD
= 25oC, VREF+ = 2V, VDD = VAA+ = 5V, VAA- = VREF - = VSS = GND, fCLK = 25MHz Unless Otherwise Specified (Continued) TEST CONDITIONS (Note 4) MIN TYP 25 40 MAX fCLK/2 UNITS MHz
PARAMETER Allowable Input Bandwidth -3dB Input Bandwidth REFERENCE INPUTS Input Range VREF+ Range VREF- Range Input Loading DIGITAL INPUTS Digital Input Maximum VIN, Low CLOCK CE1, CE2 Minimum VIN, High CLOCK CE1, CE2 Input Leakage, Except CLK Input Leakage, CLK DIGITAL OUTPUTS Digital Outputs Output Low (Sink) Current Output High (Source) Current Three-State Leakage Current TIMING CHARACTERISTICS Conversion Timing Maximum Conversion Speed Auto-Balance Time (1) Sample Time (2) Output Timing Data Valid Delay Data Hold Time Output Enable Time Output Disable Time POWER SUPPLY CHARACTERISTICS Device Current, IAA Resistor Ladder ImpedanceDevice Current, IDD VAA+ = 5V, VSS CE1 = VAA- = CLK = GND VAA+ = 7V NOTES:
1. Full scale input range, VREF + - VREF may be in the range 0.5V to VAA+ -VAA- volts. Linearity errors increase at lower full scale ranges, however. 2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD voltage. 3. The CLK input is a CMOS inverter with a 50k feedback resistor. It operates from the VAA+ and VAA- supplies. It may be AC-coupled with a 1VP-P minimum source. 4. Parameter not tested, but guaranteed by design or characterization.