HomedatasheetCA3338D

CA3338D Datasheet

CMOS Video Speed, 8-bit, Flash A/D Converter
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Description

Features, Applications

Description

The is a CMOS parallel (FLASH) analog-to-digital converter designed for applications demanding both low power consumption and high speed digitization. The CA3318 operates over a wide full scale input voltage range to 7.5V with maximum power consumption depending upon the clock frequency selected. When operated from a 5V supply at a clock frequency of 15MHz, the typical power consumption of the is 150mW. The intrinsic high conversion rate makes the CA3318 ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3318s in series to increase the resolution of the conversion system. A series connection of two CA3318s may be used to produce a 9-bit high speed converter. Operation of two CA3318s in parallel doubles the conversion speed (i.e., increases the sampling rate from 30MHz). 256 paralleled auto balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3318. 255 comparators are required to quantize all input voltage levels in this 8-bit converter, and the additional comparator is required for the overflow bit.

Features

CMOS Low Power with SOS Speed (Typ). 150mW Parallel Conversion Technique 15MHz Sampling Rate (Conversion Time). 67ns 8-Bit Latched Three-State Output with Overflow Bit Accuracy (Typ). �1 LSB Single Supply Voltage. 7.5V 2 Units in Series Allow 9-Bit Output 2 Units in Parallel Allow 30MHz Sampling Rate

Applications

TV Video Digitizing (Industrial/Security/Broadcast) High Speed A/D Conversion Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research General-Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis �P Data Acquisition Systems

PART NUMBER LINEARITY (INL, DNL) CA3318CD �1.5 LSB �1.5 LSB �1.5 LSB SAMPLING RATE 15MHz (67ns) TEMP. RANGE (oC) to 85 PACKAGE 24 Ld PDIP 24 Ld SOIC 24 Ld SBDIP PKG. NO. M24.3 D24.6

24 VAA + (ANA. SUP.) 3/4R 22 VREF + 21 VIN p 19 PHASE 18 CLK 17 VAA - (ANA. GND) 16 VIN 15 VREF 13 CE2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999

VAA+ 24 VIN 21 VREF R 22 CAB = 2 LATCH 256 LATCH 256 ENCODER LOGIC ARRAY COUNT 256 ANALOG SUPPLY
THREESTATE OUTPUT REGISTER DRIVERS OVERFLOW D Q CLK BIT 8 (MSB) D Q CLK BIT D Q CLK 8 9

DC Supply Voltage Range (VDD or VAA+). to +8V (Referenced to VSS or VAA- Terminal, Whichever is More Negative) Input Voltage Range CE2 and CE1. VAA- -0.5V to VDD + 0.5V Clock, Phase, VREF 1/2 Ref. VAA- -0.5V to VAA+ + 0.5V Clock, Phase, VREF 1/4 Ref. VSS- -0.5V to VDD + 0.5V VIN , 3/4 REF, VREF VAA- -0.5V to VAA- + 7.5V Output Voltage Range,. VSS 0.5V to VDD + 0.5V Bits 1-8, Overflow (Outputs Off) DC Input Current. �20mA Clock, Phase, CE1, CE2, VIN , Bits 1-8, Overflow

Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) SBDIP Package. 60 22 PDIP Package. 60 N/A SOIC Package. 75 N/A Maximum Junction Temperature Ceramic Package. 175oC Plastic Packages. 150oC Maximum Storage Temperature to 150oC Maximum Lead Temperature (Soldering 10s). 265oC (SOIC - Lead Tips Only)

Operating Voltage Range (VDD or VAA+). 4V (Min) to 7.5V (Max) Recommended VAA + Operating Range. VDD �1V Recommended VAA - Operating Range. VSS �1V Operating Temperature Range (TA). to 85oC

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: JA is measured with the component mounted on an evaluation PC board in free air.

PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error Differential Linearity Error Offset Error, Unadjusted Gain Error Unadjusted DYNAMIC CHARACTERISTICS Maximum Input Bandwidth Maximum Conversion Speed Signal to Noise Ratio (SNR) RMSSignal = -------------------------------RMSNoise Signal to Noise Ratio (SINAD) RMSSignal = ----------------------------------------------------------RMSNoise+Distortion Total Harmonic Distortion, THD Effective Number of Bits (ENOB) Differential Gain Error Differential Phase Error ANALOG INPUTS

At 25oC, VAA+ = VDD = 5V, VREF = 6.4V, VREF - = VAA- = VSS , CLK = 15MHz, All Reference Points Adjusted, Unless Otherwise Specified TEST CONDITIONS MIN 8 VIN = VREF- + 1/2 LSB VIN = VREF+ - 1/2 LSB (Note 1) CA3318 CLK = Square Wave = 15MHz, fIN = 15MHz, fIN = 15MHz, fIN = 15MHz, fIN = 15MHz, fIN = 15MHz, fIN = 15MHz, fIN = 15MHz, fIN = 4MHz Unadjusted Notes 2, 4 VIN = 5V, VREF+ -0.5 -1.5 TYP 4.5 0 MAX UNITS Bits LSB

Full Scale Range, VIN and (VREF+) - (VREF Input Capacitance, VIN Input Current, VIN , (See Text) REFERENCE INPUTS Ladder Impedance


Features

Parameters


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