|64K-bit I2C Serial EEPROM with Partial Array Write Protection
400kHz I2C Bus to 5.5V supply voltage range Cascadable for up to eight devices 32-byte page write buffer Self-timed write cycle with auto-clear Schmitt trigger inputs for noise protection Write protection Top 1/4 array protected when WP at VIH 1,000,000 program/erase cycles 100 year data retention Industrial and automotive temperature ranges RoHS-compliant packagesDESCRIPTION
The a 64K-bit Serial CMOS EEPROM internally organized as 8192 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT24WC66 features a 32-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.
Pin Name A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect Power Supply Ground* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
� 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS(1) Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground VCC with Respect to Ground Package Power Dissipation Capability (TA = 25�C) Lead Soldering Temperature (10 secs) Output Short Circuit CurrentParameter Endurance Data Retention ESD Susceptibility Latch-up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS VCC to 5.5V, unless otherwise specified. Symbol ICC ISB(6) ILI ILO VIL VIH VOL1 VOL2 Parameter Power Supply Current Standby Current (VCC = 5V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = +3.0V) Output Low Voltage(VCC = +1.8V) IOL 3.0 mA IOL 1.5 mA Test Conditions fSCL = 100kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -1 VCC x 0.7 Min Typ Max VCC x 0.3 VCC Units mA �AParameter Input/Output Capacitance (SDA) Input Capacitance A1, A2, SCL, WP)
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V. (6) Maximum standby current (ISB) = 10�A for the Automotive and Extended Automotive temperature range.
AC CHARACTERISTICS VCC to 5.5V, unless otherwise specified. Output Load is 1TTL Gate and 100pF. Memory Read & Write Cycle Limits Symbol FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
Power-Up Timing (1) (2) Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Write Operation Min Typ Max 1 Units ms
Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min Typ Max 10 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.