s SPI bus compatible s Low power CMOS technology to 6.0V operation s Self-timed write cycle with auto-clear s Hardware reset pin s Hardware and software write protection s Commercial, industrial and automotive
s Power-up inadvertant write protection s RDY/BSY pin for end-of-write indication s 1,000,000 program/erase cycles s 100 year data retentionDESCRIPTION
The a 1K/2K/4K-bit Serial EEPROM which is configured as 64/128/256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC10/20/40 is manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, SOIC and TSSOP packages.
Pin Name DI DO VCC GND RESET RDY/BUSY Function Chip Select Clock Input Serial Data Input Serial Data Output to +6.0V Power Supply Ground Reset Ready/BUSY StatusDATA REGISTER DI RESET CS MODE DECODE LOGIC OUTPUT BUFFER
2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Temperature Under Bias................. to +125�C Storage Temperature....................... to +150�C Voltage on any Pin with Respect �2.0V to +VCC +2.0V VCC with Respect to Ground............... to +7.0V Package Power Dissipation Capability (Ta 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17Test Input/Output Capacitance (DO, RDY/BSY) Input Capacitance (CS, SK, DI, RESET)
Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V.
D.C. OPERATING CHARACTERISTICS VCC to +6.0V, unless otherwise specified. Limits Sym. ICC Parameter Operating Current 2.5V Min. Typ. Max. VCC 0.7 �0.1 VCC 2.5V 6.0V VCC � 0.3 VCC 2.4 VOL(2) Low Level Output Voltage 6.0V 0.4 VCC x 0.3 VCC + 0.5 VCC x 0.2 VCC + 0.5 Units mA �A IOH = �10�A IOH = �10�A IOH = �400�A IOL = 10�A IOL = 2.1mA VIN = GND or VCC CS = VCC VIN = GND to VCC VOUT = GND to VCC Test Conditions fSK = 250 kHz fSK = 1 MHz
EWEN, EWDS, READ 6.0V ICCP ISB(1) ILI ILO VIL VIH VIL VIH Program Current 2.5V 6.0V Standby Current Input Leakage Current Output Leakage Current Low Level Input Voltage, DI High Level Input Voltage, DI Low Level Input Voltage, CS, SK, RESET High Level Input Voltage, CS, SK, RESETNote: (1) Standby Current (ISB) (<900nA) (2) VOH and VOL spec applies to READY/BUSY pin also