s 10 MHz SPI compatible to 6.0 volt operation s Hardware and software protection s Zero standby current s Low power CMOS technology s SPI modes 1,1)* s Commercial, industrial, automotive and extended s 100 year data retention s Self-timed write cycles 8-pin DIP/SOIC, 8/14-pin TSSOP and 8-pin MSOP s 16/32-byte page write buffer s Write protection
� Protect first page, last page, any 1/4 array or lower 1/2 array
The a 1K/2K/4K/8K/16K-Bit SPI Serial CMOS EEPROM internally organized as 128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst's advanced CMOS Technology substantially reduces device power requirements. The CAT25C11/03/05 features a 16-byte page write buffer. The 25C09/17 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C11/03/05/09/17 is designed with software and hardware write protection features including Block Write protection. The device is available in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin MSOP packages.
Serial Data Output Serial Clock Write Protect to +6.0V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input No Connect
STATUS REGISTER HIGH VOLTAGE/ TIMING CONTROL CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Temperature Under Bias................. to +125�C Storage Temperature....................... to +150�C Voltage on any Pin with Respect �2.0V to +VCC +2.0V VCC with Respect to VSS................................ to +7.0V Package Power Dissipation Capability (Ta 25�C)................................... 1.0W Lead Soldering Temperature (10 secs)............ 300�C Output Short Circuit 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS VCC to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB ILI ILO VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 VCC x 0.7 Min. Typ. Max. VCC x 0.3 VCC 0.5 0.4 Units �A 2.7VVCC<5.5V IOL = 3.0mA IOH -1.6mA 1.8VVCC<2.7V IOL = 150�A IOH = -100�A VOUT 0V to VCC, = 0V Test Conditions VCC @ 5MHz SO=open; CS=Vss VCC = 5.5V FCLK CS = VCC VIN = VSS or VCC
Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V. (5) VILMIN and VIHMAX are reference values only and are not tested.
Applicable over recommended operating range from TA=25�C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD)
A.C. CHARACTERISTICS Limits 1.8V-6.0V SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tWC(3) tV tHO tDIS tHZ tCS tCSS tCSH tWPS tCSH
Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time CS Hold Time
This parameter is tested initially and after a design or process change that affects the parameter. AC Test Conditions: Input Pulse Voltages: to 0.7VCC Input rise and fall times: 10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; = 50pF tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.