Quad Digitally Programmable Potentiometers (DPPTM) with 64 Taps and SPI Interface
s 64 resistor taps per potentiometer s End to end resistance 100k s Potentiometer control and memory access via
to 6.0 volt operation s Standby current less than s 1,000,000 nonvolatile WRITE cycles s 100 year nonvolatile memory data retention s 24-lead SOIC, 24-lead TSSOP and BGA s Commercial and industrial temperature rangess Low wiper resistance, typically 80 s Nonvolatile memory storage for up to four wiper
The CAT5401 is four Digitally Programmable Potentiometers (DPPsTM) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a SPI serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register. The CAT5401 can be used as a potentiometer as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. It is available in the to 70�C commercial and to 85�C industrial operating temperature ranges and offered a 24-lead SOIC and TSSOP package or in the chip scale BGA.
SOIC Package (J, W) VCC RH1 RW1 GND CAT RW0 RL0 VCC A0 SO HOLD SCK RH1 RW1 GND RH2 RL2 SCK HOLD RH1 RH2 HOLD SCK TSSOP Package (U, RL1 RW1 VSS RW2 RL2 CAT RH0 RL0 VCC A0 SO2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Chip Select Write Protection Serial Input Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground No Connect Wiper Terminal for Potentiometer 2 High Reference Terminal for Potentiometer 2 Low Reference Terminal for Potentiometer 2 Bus Serial Clock Hold Serial Data Output Device Address, LSB Wiper Terminal for Potentiometer 3
SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses and data to be written to the CAT5401. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT5401. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT5401. Opcodes, byte addresses or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. A0, A1: Device Address Inputs These inputs set the device address when addressing multiple devices. When these pins are left floating the default values are zero. A total of four devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5401. RH, RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer.
CS: Chip Select CS is the Chip select pin. CS low enables the D2 RH3 High Reference Terminal CAT5401 and CS high disables the CAT5401. CS high for Potentiometer 3 takes the SO output pin to high impedance and forces E1 RL3 Low Reference Terminal the devices into a Standby mode (unless an internal for Potentiometer 3 write operation is underway). The CAT5401 draws ZERO current in the Standby mode. A high to low NC No Connect transition CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all write operations to the wiper control and Data registers are inhibited. WP going low while CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. HOLD: Hold The HOLD pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor.
The CAT5041 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT5401 to interface directly with many of today's popular microcontrollers. The CAT5041 contains an 8-bit instruction register.The instruction set and the operation codes are detailed in the instruction set table 3. After the device is selected with CS going low the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed.
The CAT5401 is four resistor arrays integrated with SPI serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the SPI bus. Additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.