HomedatasheetCAT93C5631

CAT93C5631 Datasheet

Supervisory Circuits With Microwire Serial CMOS E2PROM, Precision Reset Controller And Watchdog Timer
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Description

Features, Applications

Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

FEATURES

s Watchdog Timer s Programmable Reset Threshold s Built-in Inadvertent Write Protection s Active High or Low Reset Outputs

--Precision Power Supply Voltage Monitoring --5V, 3.3V and 3V options

s Hardware and Software Write Protection s Power-Up Inadvertant Write Protection s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial, and Automotive

s High Speed Operation: 3MHz s Low Power CMOS Technology x 8 Selectable Serial Memory s Self-Timed Write Cycle with Auto-Clear s Sequential Read s Fast Nonvolatile Write Cycle: 3ms Max

DESCRIPTION

The is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The serial EEPROM memory of the 93CXXXX can be configured either by 8-bits. Each register can be written (or read) by using the DI (or DO pin). The reset function of the 93CXXXX protects the system during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. Catalyst's advanced CMOS technology substantially reduces device power requirements. The 93CXXXX is available in 8-pin DIP, 8pin TSSOP or 8-pin SOIC packages. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years.

Pin Name CS RESET/RESET DI DO VCC GND ORG Function Chip Select Reset I/O Clock Input Serial Data Input

DATA REGISTER DI MODE DECODE LOGIC OUTPUT BUFFER
Serial Data Output to 6.0V Power Supply Ground Memory Organization

Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization.

1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

Temperature Under to +125�C Storage Temperature........................ to +150�C Voltage on Any Pin with Respect Ground(1)..............�2.0V to +VCC + 2.0V VCC with Respect to +7.0V Package Power Dissipation Capability (Ta = 25�C)1.0W.................................1.0W Lead Soldering Temperature (10 secs)...............300�C Output Short Circuit Current(2)..........................100mA

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

D.C. OPERATING CHARACTERISTICS VCC to +6.0V, unless otherwise specified. Limits Symbol ISB1 ISB2 ILI ILO VOL1 VOH1 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -0.1 2 Min. Typ. Max. VCC+1 0.4 Units V 4.5VVCC<5.5V IOL = 2.1mA IOH = -400�A Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 0V ORG=GND CS=0V ORG=Float or VCC VIN 0V to VCC VOUT 0V to VCC, 0V 4.5VVCC<5.5V

Note: (1) The minimum DC input voltage is �0.5V. During transitions, inputs may undershoot to �2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time.

Symbol VZAP(1) ILTH(1)(3) Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17

to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF

Limits VCC 2.7V -6V SYMBOL PARAMETER tCSS tCSH tDIS tDIH tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC Min. Max. VCC = 4.5V-5.5V Min. ms �s KHZ = 100pF Test

Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 Units ms

Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) Latch-up protection is provided for stresses mA on address and data pins from �1V to VCC +1V.


Features

Parameters


Manufacturer information

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