Product data File under Integrated Circuits ICL03 2001 Dec 12
The CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated Output Enable (OE) input is HIGH.FEATURES
Standard '125-type pinout (D, DB, and PW packages) 5 switch connection between two ports TTL-compatible input levels Latch-up testing is done to JESDEC Standard JESD78 which
PACKAGES 14-Pin Plastic SO 14-Pin Plastic SSOP 16-Pin Plastic SSOP(QSOP) 14-Pin Plastic TSSOP TEMPERATURE RANGE +85 �C ORDER CODE CBT3125DS CBT3125PW DRAWING NUMBER SOT519-1 SOT402-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.Pin numbers shown are for 14-pin package-types. Figure 3. CBT3125 logic diagram (positive logic)
Over operating free-air temperature range, unless otherwise noted. SYMBOL VCC VI IK Tstg supply voltage range input voltage range continuous channel current input clamp current storage temperature range VI/O < 0 see Note 2 PARAMETER CONDITIONS MIN. �0.5 �65 MAX. UNIT mA �C
NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
SYMBOL VCC VIH VIL Tamb supply voltage high-level control input voltage low-level control input voltage operating ambient temperature in free-air PARAMETER CONDITIONS MIN. 2 �40 MAX. 0.8 +85 UNIT V �C
NOTE: 1. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.