HomedatasheetCD3206BB

CD3206BB Datasheet

9-bit Latched/registered/pass-thru Futurebus Transceiver
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Description

Features, Applications

FEATURES
Drives heavily loaded backplanes with High drive 100mA BTL open collector
provides accurate receiver thresholds and improved noise immunity

Glitch-free power up/power down operation Low ICC current Tight output skew Supports live insertion

SYMBOL tPLH tPHL tPLH tPHL CO IOL Propagation delay to Bn Propagation delay to An Output capacitance � Bn only) Output current � Bn only) AIn to Bn (outputs Low or High) ICC S Supply l current Bn to AOn (outputs Low) Bn to AOn (outputs High) PARAMETER TYPICAL UNIT pF mA

PACKAGE 52-pin Plastic Quad Flat Pack (QFP) COMMERCIAL RANGE VCC = 5V�10%; Tamb +70�C FB2031BB INDUSTRIAL RANGE VCC = 5V�10%; Tamb +85�C CD3206BB DRAWING NUMBER SOT379-1

LOGIC GND A2 LOGIC GND A3 LOGIC GND A4 LOGIC GND A5 LOGIC GND A6 LOGIC GND A7 LOGIC GND A8 SEL1 TDI (option) TDO (option) BUS GND BG GND BG VCC LCBA LCAB SEL0 VCC B8 B7 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND

DESCRIPTION

The a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FB2031 is intended to provide the electrical interface to a high performance wired-OR bus. The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and A "00" configures latches in both directions. A "10" configures thru mode in both directions. A "01" configures register mode in both directions. A "11" configures register mode in the A-to-B direction and latch mode in the B-to-A direction. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled.

When either OEB0 is Low OEB1 is High, the B port is inactive and is pulled to the level of the pullup voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are 3-State (A port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The "VOH" clamp reduces inductive ringing effects during a Low-to-High transition. The "VOH" clamp is always active. The other clamp, the "trapped reflection" clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition.

To support live insertion, OEB0 is held Low during power on/off cycles to insure glitchfree B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.

PARAMETER ja jc CONDITION Still air 300 Linear feet per minute air flow Thermally mounted on one side to heat sink 52-PIN PLASTIC QFP 58�C/W 20�C/W

SYMBOL OEB0 OEB1 OEA BUS GND LOGIC GND VCC BIAS V BG VCC BG GND SEL0 SEL1 LCAB LCBA TMS TCK TDI TDO PIN NUMBER TYPE I/O Input GND Power GND Input Output NAME AND FUNCTION BiCMOS data inputs/3-State outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the A outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Live insertion pre-bias pin Band Gap threshold voltage reference Band Gap threshold voltage reference ground Mode select Mode select to B clock/latch enable (transparent latch when Low) to A clock/latch enable (transparent latch when Low) Test Mode Select (optional, if not implemented then no connect) Test Clock (optional, if not implemented then no connect) Test Data In (optional, if not implemented then no connect) Test Data Out (optional, if not implemented then shorted to TDI)


Features

Parameters

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Manufacturer information

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