HomedatasheetCD4013BCJ

CD4013BCJ Datasheet

Dual D Flip-flop
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Description

Features, Applications

The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ``Q'' and ``Q'' outputs These devices can be used for shift register applications and by connecting ``Q'' output to the data input for counter and toggle applications The logic level present at the ``D'' input is transferred to the Q output during the positive-going transition of the clock pulse Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line respectively

Features
Wide supply voltage range High noise immunity Low power TTL compatibility
Applications
Automotive Data terminals Instrumentation Medical electronics
Alarm system Industrial electronics Remote metering Computers
No change e Level change x e Don't care case

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temp Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4013BM CD4013BC

Symbol IDD Parameter Quiescent Device Current Low Level Output Voltage Conditions VDD e 5V VIN e VDD or VSS VDD e 10V VIN e VDD or VSS VDD e 15V VIN e VDD or VSS

Low Level Output Current (Note 3) High Level Output Current (Note 3) Input Current
Symbol VIH Parameter High Level Input Voltage Conditions

Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The tables of ``Recommended Operating Conditions'' and ``Electrical Characteristics'' provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are measured one output at a time

Symbol CLOCK OPERATION tPHL tPLH Propagation Delay Time Parameter
Minimum Clock Pulse Width Maximum Clock Rise and Fall Time Minimum Set-Up Time

SET AND RESET OPERATION tPHL(R) tPLH(S) tWH(R) tWH(S) CIN Propagation Delay Time VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Any Input ns pF

Minimum Set and Reset Pulse Width Average Input Capacitance

Features

Parameters

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Manufacturer information

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