HomedatasheetCD40174BM

CD40174BM Datasheet

CMOS/BiCMOS->4000 Family
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Description

Features, Applications

The CD40174B consists of six positive-edge triggered D-type flip-flops the true outputs from each flip-flop are externally available The CD40175B consists of four positiveedge triggered D-type flip-flops both the true and complement outputs from each flip-flop are externally available All flip-flops are controlled by a common clock and a common clear Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse The clearing operation enabled by a negative pulse at Clear input clears all Q outputs to logical ``0'' and Qs (CD40175B only) to logical ``1'' All inputs are protected from static discharge by diode clamps to VDD and VSS

Features

Wide supply voltage range to 15V High noise immunity 0 45 VDD (typ ) Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74 LS Equivalent MC14174B MC14175B Equivalent MM74C174 MM74C175

High level Low level Irrelevant Transition from low to high level No change Q for CD40175B only

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) to 15 VDC 0V to VDD VDC

Symbol IDD Parameter Quiescent Device Current Conditions

High Level Output Current VDD 4 6V (Note 3) VDD 9 5V VDD 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V

Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The tables of ``Recommended Operating Conditions'' and ``Electrical Characteristics'' provide conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOH and IOL are tested one output at a time

Min Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V Low Level Input Voltage VDD 4 5V VDD or 9V VDD 13 5V VDD 4 5V VDD or 9V VDD 13 5V

Low Level Output Current VDD 0 4V (Note 3) VDD 0 5V VDD 1 5V High Level Output Current VDD 4 6V (Note 3) VDD 9 5V VDD 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V

e 200k and 20 ns unless otherwise specified Symbol tPHL tPLH Parameter Propagation Delay Time to a Logical ``0'' or Logical ``1'' from Clock Q (CD40175 Only) Propagation Delay Time to a Logical ``0'' from Clear to Q Propagation Delay Time to a Logical ``1'' from Clear Q (CD40175 Only) Time Prior to Clock Pulse that Data must be Present Time after Clock Pulse that Data Must be Held Transition Time Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Min Typ


Features

Parameters

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Manufacturer information

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