HomedatasheetCD4025BMS

CD4025BMS Datasheet

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Features

High-Voltage Types (20V Rating) Propagation Delay Time = 60ns (typ.) = 50pF, VDD = 10V Buffered Inputs and Outputs Standard Symmetrical Output Characteristics 100% Tested for Maximum Quiescent Current 5V, 10V and 15V Parametric Ratings Maximum Input Current at 18V Over Full Package-Temperature Range; at 18V and +25oC Noise Margin (Over Full Package Temperature Range): 1V at VDD 2V at VDD 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standards No. 13B, "Standard Specifications for Description of "B" Series CMOS Device's

Description
CD4025BMS - Dual 3 Plus Inverter - Quad 2 Input - Dual 4 Input - Triple 3 Input

CD4001BMS, CD4002BMS, and CD4025BMS NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4001BMS, CD4002BMS and the CD4025BMS is supplied in these 14 lead outline packages:

Braze Seal DIP Frit Seal DIP Ceramic Flatpack

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright � Intersil Corporation 1999



DC Supply Voltage Range, (VDD). to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs.-0.5V to VDD +0.5V DC Input Current, Any One Input.�10mA Operating Temperature Range. to +125oC Package Types K, H Storage Temperature Range (TSTG). to +150oC Lead Temperature (During Soldering). +265oC At Distance � 1/32 Inch � 0.79mm) from case for 10s Maximum

Thermal Resistance. ja jc Ceramic DIP and FRIT Package. 80oC/W 20oC/W Flatpack Package. 20oC/W o Maximum Package Power Dissipation (PD) +125 C For to +100oC (Package Type D, F, K). 500mW For to +125oC (Package Type D, F, K). Derate Linearity to 200mW Device Dissipation per Output Transistor. 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature. +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage IIL VIN = VDD or GND VDD = 18V Input Leakage IIH VIN = VDD or GND VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH10 IOH15 VNTH VPTH F VDD 15V, No Load VDD 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10�A VSS = 0V, IDD = 10�A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL 8A 8B LIMITS TEMPERATURE +25

NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

Features

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