CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register
is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering.Features
High Voltage Types (20V Rating) Bidirectional Parallel Data Input Parallel or Serial Inputs/Parallel Outputs Asynchronous or Synchronous Parallel Data Loading Parallel Data-Input Enable on "A" Data Lines (3-State Output) Data Recirculation for Register Expansion Multipackage Register Expansion Fully Static Operation DC-to-10MHz (typ.) at VDD = 10V Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current 5V, 10V and 15V Parametric Ratings Maximum Input Current at 18V Over Full Package-Temperature Range; at 18V and +25oC Noise Margin (Over Full Package Temperature Range): 1V at VDD 2V at VDD 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"Applications
Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register Shift Right/Shift Left Register Shift Right/Shift Left With Parallel Loading Address Register Buffer Register Bus System Register with Enable Parallel Lines at Bus Side Double Bus Register System Up-Down Johnson or Ring Counter Pseudo-Random Code Generators Sample and Hold Register (Storage, Counting, Display) Frequency and Phase Comparator
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright � Intersil Corporation 1999
A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B signal reverses the direction of data flow. The AE input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are enabled only when this signal is high. Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low.
A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not allowed). The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low and the AE signal is high). Register expansion can be accomplished by simply cascading CD4034BMS packages. The CD4034BMS is supplied in these 24 lead outline packages: Braze Seal DIP Ceramic Flatpack H4V H4P
DC Supply Voltage Range, (VDD). to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs.-0.5V to VDD +0.5V DC Input Current, Any One Input.�10mA Operating Temperature Range. to +125oC Package Types K, H Storage Temperature Range (TSTG). to +150oC Lead Temperature (During Soldering). +265oC At Distance � 1/32 Inch � 0.79mm) from case for 10s Maximum
Thermal Resistance. ja jc Ceramic DIP and FRIT Package. 80oC/W 20oC/W Flatpack Package. 20oC/W o Maximum Package Power Dissipation (PD) +125 C For to +100oC (Package Type D, F, K). 500mW For to +125oC (Package Type D, F, K). Derate Linearity to 200mW Device Dissipation per Output Transistor. 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature. +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current Except A and B Lines IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current Except A and B Lines IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH10 IOH15 VNTH VPTH F VDD 15V, No Load VDD 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10�A VSS = 0V, IDD = 10�A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 8B +25oC, LIMITS TEMPERATURE +125oC -55oC3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.