CD4042BDTG4 Datasheet



CD4042BDTG4 types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit, The impedance of then. and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and b during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY - 1 the transfer occurs during the I CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY - 0 and negative for POLARITY - 1) the information present at the input during the CLOCK transition is retained at the outputs until an opposite CLOCK transition occurs. CD4042BDTG4 Features • Clock polarity control• 0 and rI outputs• Common clock• Low power TTL compatible• Standardized symmetrical output characteristics• 100% tested for quiescent current at 20 V• Maximum input current of 1 yA at 18 V over full package-temperature range; 100 nA at 18Vand250C• 5-V, 10-V, and 15-V parametric ratings• Noise margin (over full package temperature range): 1 VatVDD=5V 2VatVDD-10V 2.5 VatVDD=15V• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B Series CMOS Devices" CD4042BDTG4 Application • Buffer storage• Holding register• General digital logic


[{"Name":"Number of Output Lines","Value":"4"},{"Name":"High Level Output Current","Value":"- 4.2 mA"},{"Name":"Low Level Output Current","Value":"32 mA"},{"Name":"Propagation Delay Time","Value":"300 ns at 5 V, 150 ns at 10 V, 100 ns at 15 V"},{"Name":"Supply Voltage - Ma","Value":"18 V"},{"Name":"Supply Voltage - Min","Value":"3 V"},{"Name":"Maximum Operating Temperature","Value":"+ 125 C"},{"Name":"Minimum Operating Temperature","Value":"- 55 C"},{"Name":"","Value":""},{"Name":"","Value":""}]

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