The CD4541BC Programmable Timer is designed with a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, output control logic, and a special power-on reset circuit. The special features of the power-on reset circuit are first, no additional static power consumption and second, the part functions across the full voltage range (3V�15V) whether power-on reset is enabled or disabled. Timing and the counter are initialized by turning on power, if the power-on reset is enabled. When the power is already on, an external reset pulse will also initialize the timing and counter. After either reset is accomplished, the oscillator frequency is determined by the external RC network. The 16-stage counter divides the oscillator frequency by any of 4 digitally controlled division ratios.Features
s Available division ratios 216 s Increments on positive edge clock transitions s Built-in low power RC oscillator (�2% accuracy over temperature range and �10% supply and �3% over processing < 10 kHz) s Oscillator frequency range to 100 kHz s Oscillator may be bypassed if external clock is available (apply external clock to pin 3) s Automatic reset initializes all counters when power turns on s External master reset totally independent of automatic reset operation s Operates at 2n frequency divider or single transition timer s Q/Q select provides output logic level flexibility s Reset (auto or master) disables oscillator during resetting to provide no active power dissipation s Clock conditioning circuit permits operation with very slow clock rise and fall times s Wide supply voltage 15V s High noise immunity--0.45 VDD (typ.) s 5V�10V�15V parameter ratings s Symmetrical output characteristics s Maximum input leakage at 15V over full temperature range s High output drive (pin 8) min. one TTL load
Order Number CD4541BCM CD4541BCN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pin Auto Reset Operating Timer Operational Output Initially Low after Reset Single Cycle Mode State 1 Auto Reset Disabled Master Reset On Output Initially High after Reset Recycle Mode
With Auto Reset pin set a "0" the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set a "1". Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.: However, when is "0", normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 28). The Q/Q select output control pin provides for a choice of output level. When the counter in a reset condition and Q/Q select pin is set a "0" the Q output a "0". Correspondingly, when Q/Q select pin is set a "1" the Q output a "1". When the mode control pin is set a "1", the selected count is continually transmitted to the output. But, with mode pin "0" and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after 2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation.
and RS 2 Rtc where 10 k The time select inputs (A and B) provide a two-bit address to output any one of four counter stages 210, 213, and 216). The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter. When 216 is selected for both states of B.
Solid Line = RTC 1 k and = 10.2 kHz @ VDD = 10V and = 25� Dashed Line = RTC 120 k and = 7.75 kHz @ VDD = 10V and = 25� Line as a function of C and (RTC = 120k Line as a function of RTC and = 100 pF; TC