CD74AC191E Datasheet

Presettable Synchronous 4-bit Binary Up/down Counter


Features, Applications
Data sheet acquired from Harris Semiconductor SCHS243

The CD74AC191 and CD74ACT191 are asynchronously presettable binary up/down synchronous counters that utilize the Harris Advanced CMOS Logic technology. Presetting the counter to the number on preset data inputs (P0-P3) is accomplished by setting LOW the asynchronous parallel load input (PL). Counting occurs when PL is HIGH, Count Enable (CE) is LOW, and the Up/Down (U/D) input is either LOW for up-counting or HIGH for down-counting. The counter is incremented or decremented synchronously with the LOW-to-HIGH transition of the clock. When an overflow or underflow of the counter occurs, the Terminal Count (TC) output, which is LOW during counting, goes HIGH and remains HIGH for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 12). The TC output also initiates the Ripple Clock (RC) output which, normally HIGH, goes LOW and remains LOW for the low-level cascaded using the Ripple Count output.


Typical Propagation Delay 12.8ns at VCC = 50pF Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature to 5.5V Operation and Balanced Noise Immunity 30% of the Supply �24mA Output Drive Current - Fanout to 15 FASTTM ICs - Drives 50 Transmission Lines

PART NUMBER CD74AC191M CD74ACT191M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) PACKAGE PKG. NO. E16.3 M16.15

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FASTTM is a Trademark of Fairchild Semiconductor. Copyright � Harris Corporation 1998

TRUTH TABLE INPUTS PL CE U/D CP X FUNCTION Count Up Count Down Asynchronous Preset No Change
U/D or CE should be changed only when clock is high. X = Don't Care = Low-to-High clock transition.

DC Supply Voltage, VCC. 6V DC Input Diode Current, IIK For VI > VCC 0.5V.�20mA DC Output Diode Current, IOK For VO > VCC 0.5V.�50mA DC Output Source or Sink Current per Output Pin, IO For VO < VCC 0.5V.�50mA DC VCC or Ground Current, ICC or IGND (Note 3).�100mA

Thermal Resistance (Typical, Note 5) JA (oC/W) PDIP Package. SOIC Package. Maximum Junction Temperature (Hermetic Package or Die). 175oC Maximum Storage Temperature to 150oC Maximum Lead Temperature (Soldering 10s). 300oC

Temperature Range, TA. to 125oC Supply Voltage Range, VCC (Note to 5.5V ACT 5.5V DC Input or Output Voltage, VI, VO. 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 3V. 50ns (Max) AC Types, 5.5V. 20ns (Max) ACT Types, 5.5V. 10ns (Max)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES: 3. For to 4 outputs per device, add �25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. JA is measured with the component mounted on an evaluation PC board in free air.

TEST CONDITIONS PARAMETER AC TYPES High Level Input Voltage VIH 3 5.5 Low Level Input Voltage VIL 3 5.5 High Level Output Voltage VOH VIH or VIL (Note 7) -50 (Note SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN MAX TO 85oC MIN MAX TO 125oC MIN MAX UNITS



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