|Data sheet acquired from Harris Semiconductor SCHS272
FCT Interface Logic Octal Transparent Latch, Three-State
The CD54/74FCT373, 373AT, and 533 octal transparent latches use a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output-HIGH level to two diode drops below VCC. This resultant lowering of output swing to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking to 48mA. The CD54/74FCT373, 373AT, and 533 outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the highimpedance state. The latch operation is independent of the state of the Output Enable.Features
CD54/74FCT373AT - Non-Inverting CD54/74FCT533 - Inverting Buffered inputs Typical Propagation Delay: 3.9ns at VCC 50pF (FCT373AT) SCR-Latchup-Resistant BiCMOS Process and Circuit Design FCTXXX Types - Speed of Bipolar FAST�/AS/S; FCTXXXAT Types - 30% Faster than FAST/AS/S with Significantly Reduced Power Consumption to 32mA Output Sink Current (Commercial/ Extended Industrial) Output Voltage Swing Limited 3.7V at VCC = 5V Controlled Output-Edge Rates Input/Output Isolation to VCC BiCMOS Technology with Low Quiescent Power
PART NUMBER CD54FCT373H CD54FCT533H TEMP. RANGE (oC) to 125 PACKAGE 20 Ld PDIP 20 Ld PDIP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld SOIC 20 Ld SSOP 20 Ld SSOPH = HIGH voltage level. L = LOW voltage level. X = Irrelevant. Z = HIGH Impedance.
I = LOW voltage level one setup time prior to the high-to-low latch enable transition. h = HIGH voltage level one setup time prior to the high-to-low latch enable transition.FAST� is a registered trademark of Fairchild Semiconductor Corporation.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
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