HomedatasheetCD74FCT543M96

CD74FCT543M96 Datasheet

Registered Transceivers
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CD74FCT543 BiCMOS OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

BiCMOS Technology With Low Quiescent Power Buffered Inputs Inverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 64-mA Output Sink Current Output Voltage Swing Limited 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit Design Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (EN) DIP

description

The is an octal register/transceiver with 3-state outputs that uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from to B, for example, the A-to-B enable (CEAB) input must be low to enter data from or to take data from to B8. When CEAB is low, a low signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present at the output of the A latches. Control of data from A is similar, but uses the CEBA, LEBA, and OEBA inputs. The CD74FCT543 contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from A is similar but requires using the CEBA, LEBA, and OEBA inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The CD74FCT543 is characterized for operation from to 70�C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

FUNCTION TABLE INPUTS CEAB LEAB OEAB LATCH STATUS Storing � Storing Transparent OUTPUT B0 L

Transparent H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established

� This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
OEBA CEBA LEBA OEAB CEAB LEAB 22 B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

DC supply voltage range, VCC. V DC input clamp current, IIK (VI < �0.5 V). mA DC output clamp current, IOK (VO < �0.5 V). mA DC output sink current per output pin, IOL. mA DC output source current per output pin, IOH. �30 mA Continuous current through VCC, ICC. 140 mA Continuous current through GND. 528 mA Package thermal impedance, JA (see Note 1): EN package. 67�C/W M package. 46�C/W SM package. 61�C/W Storage temperature range, Tstg. to 150�C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.


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