|Data sheet acquired from Harris Semiconductor SCHS164F
High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
The 'HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR) pin.Features [ /Title CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit
Four Operating Modes - Shift Right, Shift Left, Hold and Reset Synchronous Parallel or Serial Operation Typical fMAX 60MHz at VCC = 25oC Asynchronous Master Reset Fanout (Over Temperature Range) - Standard Outputs. 10 LSTTL Loads - Bus Driver Outputs. 15 LSTTL Loads Wide Operating Temperature Range. to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types to 6V Operation - High Noise Immunity: NIL = 30%, NIH 30% of VCC at VCC = 5V HCT Types to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, 1�A at VOL, VOH
PART NUMBER CD74HC194PW CD74HC194PWR TEMP. RANGE (oC) to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIPCD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) TOP VIEW
NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Hold (Do Nothing) Shift Left CP X Shift Right Parallel Load X l (Note h l (Note 1) l (Note X l (Note 1) l (Note 1) l (Note 1) h DSR DSL H d0 OUTPUT q2 d3
H = High Voltage Level, h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition, L = Low Voltage Level, l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition, dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock Transition, X = Don't Care, = Transition from Low to High Level NOTE: 1. The High-to-Low transition of the S0 and S1 Inputs on the 'HC194 and CD74HCT194 should take place only while CP is High for Conventional Operation.
DC Supply Voltage, VCC. 7V DC Input Diode Current, IIK For VI > VCC 0.5V.�20mA DC Output Diode Current, IOK For VO > VCC 0.5V.�20mA DC Output Source or Sink Current per Output Pin, IO For VO < VCC 0.5V.�25mA DC VCC or Ground Current, ICC or IGND.�50mA
Package Thermal Impedance, JA (see Note 2): E (PDIP) Package. 67oC/W M (SOIC) Package. 73oC/W NS (SOP) Package. 64oC/W PW (TSSOP) Package. 108oC/W Maximum Junction Temperature. 150oC Maximum Storage Temperature to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)
Temperature Range (TA). to 125oC Supply Voltage Range, VCC to 6V HCT 5.5V DC Input or Output Voltage, VI, VO. 0V to VCC Input Rise and Fall Time 2V. 1000ns (Max) 4.5V. 500ns (Max) 6V. 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7.
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 4.5 6 Low Level Input Voltage VIL 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX TO 85oC MIN MAX TO 125oC MIN MAX UNITS