HomedatasheetCD74HCT174W

CD74HCT174W Datasheet

High Speed CMOS Logic Hex D-type Flip-flop With Reset
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Description

Features, Applications
Data sheet acquired from Harris Semiconductor SCHS159
High Speed CMOS Logic Hex D-Type Flip-Flop with Reset
Description

The Harris CD74HC174 and CD74HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The CD74HCT174 is functional as well as, pin compatible to the 74LS174.

Features

Buffered Positive Edge Triggered Clock Asynchronous Common Reset Fanout (Over Temperature Range) - Standard Outputs. 10 LSTTL Loads - Bus Driver Outputs. 15 LSTTL Loads Wide Operating Temperature Range. to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types to 6V Operation - High Noise Immunity: NIL = 30%, NIH 30% of VCC at VCC = 5V HCT Types to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, 1�A at VOL, VOH

[ /Title HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop

PART NUMBER CD74HCT174M CD74HCT174W NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Wafer PKG. NO. E16.3 M16.15

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

TRUTH TABLE INPUTS RESET (MR) CLOCK X L DATA Dn OUTPUT L Q0

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established

DC Supply Voltage, VCC. 7V DC Input Diode Current, IIK For VI > VCC 0.5V.�20mA DC Output Diode Current, IOK For VO > VCC 0.5V.�20mA DC Output Source or Sink Current per Output Pin, IO For VO < VCC 0.5V.�25mA DC VCC or Ground Current, ICC or IGND.�50mA

Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package. 85 SOIC Package. 110 Maximum Junction Temperature. 150oC Maximum Storage Temperature to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)

Temperature Range (TA). to 125oC Supply Voltage Range, VCC to 6V HCT 5.5V DC Input or Output Voltage, VI, VO. 0V to VCC Input Rise and Fall Time 2V. 1000ns (Max) 4.5V. 500ns (Max) 6V. 400ns (Max)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: JA is measured with the component mounted on an evaluation PC board in free air.

TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 4.5 6 Low Level Input Voltage VIL 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL �A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX TO +85oC MIN MAX TO 125oC MIN MAX UNITS


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