HomedatasheetCD82C55A

CD82C55A Datasheet

CMOS Programmable Peripheral Interface
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Description

Features, Applications

Description

The Intersil is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power.

Features

Pin Compatible with NMOS 8255A 24 Programmable I/O Pins Fully TTL Compatible High Speed, No "Wait State" Operation with 5MHz and 8MHz 80C86 and 80C88 Direct Bit Set/Reset Capability Enhanced Control Word Read Capability L7 Process 2.5mA Drive Capability on All I/O Ports Low Standby Power (ICCSB).10�A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999

SYMBOL VCC GND D0-D7 RESET WR A0-A1 PIN NUMBER I/O TYPE DESCRIPTION VCC: The +5V power supply pin. A 0.1�F capacitor between pins 26 and 7 is recommended for decoupling. GROUND DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the "Bus Hold" circuitry turned on. CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port. PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.

BI-DIRECTIONAL DATA BUS D7-D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS
GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4)

Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A "low" on this input pin enables the communcation between the 82C55A and the CPU. (RD) Read. A "low" on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 82C55A. (WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 82C55A. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1).

82C55A BASIC OPERATION INPUT OPERATION (READ) Port A Data Bus Port B Data Bus Port C Data Bus Control Word Data Bus OUTPUT OPERATION (WRITE) Data Bus Port A Data Bus Port B Data Bus Port C Data Bus Control DISABLE FUNCTION Data Bus Three-State Data Bus Three-State

CS POWER SUPPLIES +5V GND GROUP A CONTROL GROUP A PORT A (8) I/O PA7PA0
GROUP A PORT C UPPER (4) 8-BIT INTERNAL DATA BUS GROUP B PORT C LOWER (4)
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP & B CONTROL LOGIC FUNCTIONS

(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. "Bus hold" devices internal to the 82C55A will hold the I/O port inputs to a logic "1" state with a maximum hold current of 400�A. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 82C55A. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper - C4) Control Group B - Port B and Port C lower - C0) The control word register can be both written and read as shown in the "Basic Operation" table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic "1", as this implies control word mode information.


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