HomedatasheetCDB4396

CDB4396 Datasheet

24-bit, 192 KHZ D/A Converter For Digital Audio
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Description

The is a complete high performance 24-bit 48/96/192 kHz stereo digital-to-analog conversion system. The device includes a digital interpolation filter followed by a oversampled multi-bit delta-sigma modulator which drives dynamic-element-matching (DEM) selection logic. The output from the DEM block controls the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture features significantly lower out-of-band noise and jitter sensitivity than traditional 1-bit designs, and the advanced DEM guarantees low noise and distortion at all signal levels. ORDERING INFORMATION C 28-pin Plastic SOIC CDB4397 Evaluation Board

Bit Conversion to 192 kHz Sample Rates 120 dB Dynamic Range -100 dB THD+N l Advanced Dynamic-Element Matching l Low Clock Jitter Sensitivity l Digital De-emphasis for 32 kHz, 44.1 kHz and 48 kHz l External Reference Input

SCLK LRCK SDATA SERIAL INTERFACE AND FORMAT SELECT SOFT MUTE DE-EMPHASIS FILTER

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

1.0 CHARACTERISTICS/SPECIFICATIONS..................................................................... 4 ANALOG CHARACTERISTICS................................................................................... 4 Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz...................... 4 Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz.................... 4 Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz..................... 4 ANALOG CHARACTERISTICS................................................................................... 5 Power Supplies.................................................................................................... 5 Analog Output...................................................................................................... 5 Combined Digital and On-chip Analog Filter Response - Single Speed Mode.... 6 Combined Digital and On-chip Analog Filter Response - Double Speed Mode... 6 Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode..... 6 DIGITAL CHARACTERISTICS.................................................................................... 7 ABSOLUTE MAXIMUM RATINGS.............................................................................. 7 RECOMMENDED OPERATING CONDITIONS.......................................................... 7 SWITCHING CHARACTERISTICS............................................................................. 8 SWITCHING CHARACTERISTICS - CONTROL PORT............................................. 9 I2C� Mode............................................................................................................ 9 SPI Mode........................................................................................................... 10 2.0 TYPICAL CONNECTION DIAGRAM.......................................................................... 11 3.0 REGISTER DESCRIPTION........................................................................................ 12 3.1 Differential DC offset calibration........................................................................ 12 3.2 Soft Mute........................................................................................................... 12 3.3 Mode Select....................................................................................................... 13 3.4 Power DowN...................................................................................................... 13 4.0 PIN DESCRIPTION..................................................................................................... 14 5.0 APPLICATIONS.......................................................................................................... 19 5.1 Recommended Power-up Sequence................................................................. 19 6.0 CONTROL PORT INTERFACE.................................................................................. 20 6.1 SPI Mode........................................................................................................... 6.2 I2C Mode........................................................................................................... 20 6.2 Memory Address Pointer (MAP)........................................................................ 20 7.0 PARAMETER DEFINITIONS...................................................................................... 26 8.0 REFERENCES............................................................................................................ 26 9.0 PACKAGE DIMENSIONS........................................................................................... 27

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/

"The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

Figure 1. Serial Audio Input Timing........................................................................... 8 Figure 2. I2C Control Port Timing.............................................................................. 9 Figure 3. SPI Control Port Timing........................................................................... 10 Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode)....... 11 Figure 5. Control Port Timing, I2C Mode................................................................. 21 Figure 6. Control Port Timing, SPI mode................................................................ 21 Figure 7. Single-speed Transition Band.................................................................. 23 Figure 8. Single-speed Stopband Rejection............................................................ 23 Figure 9. Single-speed Transition Band.................................................................. 23 Figure 10.Single-speed Frequency Response......................................................... 23 Figure 11.Double-speed Stopband.......................................................................... 23 Figure 12.Double-speed Transition Band................................................................. 23 Figure 13.Double-speed Transition Band................................................................. 23 Figure 14.Double-speed Frequency Response........................................................ 23 Figure 15.Quad-speed Stopband Rejection............................................................. 24 Figure 16.Quad-speed Transition Band................................................................... 24 Figure 17.Quad-speed Transition Band................................................................... 24 Figure 18.Quad-speed Frequency Response.......................................................... 24 Figure 19.De-Emphasis Curve................................................................................. 24 Figure 20. Format 0, Left Justified............................................................................ 25 Figure 21. Format I2S.......................................................................................... 25 Figure 22. Format 2, Right Justified, 16-Bit Data..................................................... 25 Figure 23.Format 3, Right Justified, 24-Bit Data...................................................... 25


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