HomedatasheetCDB8952

CDB8952 Datasheet

Crystallan 100base-x and 10base-t Transceiver
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Description

Features, Applications
Features

for 100BASE-TX, 100BASE-FX and 10BASE-T ! Adaptive Equalizer provides Extended Length Operation (>160 m) with Superior Noise Immunity and NEXT Margin ! Extremely Low Transmit Jitter (<400 ps) ! Low Common Mode Noise on TX Driver for Reduced EMI Problems ! Integrated RX and TX Filters for 10BASE-T ! Compensation for Back-to-Back "Killer Packets" ! Digital Interfaces Supported

� Media Independent Interface (MII) for 100BASE-X and 10BASE-T � Repeater 5-bit code-group interface � 10BASE-T Serial Interface

LED drivers (LNK, COL, FDX, TX, RX, and SPD) ! Low power (135 mA Typ) CMOS design operates on a single 5 V supply

Description

The CS8952 uses CMOS technology to deliver a highperformance, low-cost 100BASE-X/10BASE-T Physical Layer (PHY) line interface. It makes use of an adaptive equalizer optimized for noise and near end crosstalk (NEXT) immunity to extend receiver operation to cable lengths exceeding m. In addition, the transmit circuitry has been designed to provide extremely low transmit jitter (<400 ps) for improved link partner performance. Transmit driver common mode noise has been minimized to reduce EMI for simplified FCC certification. The CS8952 incorporates a standard Media Independent Interface (MII) for easy connection to a variety of 10 and 100 Mb/s Media Access Controllers (MACs). The CS8952 also includes a pseudo-ECL interface for use with 100Base-FX fiber interconnect modules. ORDERING INFORMATION CDB8952 100-pin TQFP Evaluation Board

Register Set Compatible with DP83840A ! IEEE 802.3 Auto-Negotiation with Next Page Support
10/100 Manchester Encoder 10BaseT Filter MLT-3 Encoder Slew Rate Control

Fiber NRZI Interface Fiber NRZI Interface 10/100 4B/5B Decoder Descrambler MLT-3 Decoder 100BaseT Slicer

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

SPECIFICATIONS AND CHARACTERISTICS............................................................. 4 ABSOLUTE MAXIMUM RATINGS....................................................................... 4 RECOMMENDED OPERATING CONDITIONS................................................... 4 QUARTZ CRYSTAL REQUIREMENTS............................................................... 4 DC CHARACTERISTICS..................................................................................... 5 10BASE-T CHARACTERISTICS......................................................................... 7 100BASE-X CHARACTERISTICS....................................................................... 8 100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES........................ 9 100BASE-TX MII RECEIVE TIMING - 5B BYPASS ALIGN MODE................... 10 100BASE-TX MII TRANSMIT TIMING - 4B/5B ALIGN MODES........................ 11 100BASE-TX MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE................ 12 10BASE-T MII RECEIVE TIMING...................................................................... 13 10BASE-T MII TRANSMIT TIMING................................................................... 14 10BASE-T SERIAL RECEIVE TIMING.............................................................. 15 10BASE-T SERIAL TRANSMIT TIMING............................................................ 16 AUTO NEGOTIATION / FAST LINK PULSE TIMING........................................ 17 SERIAL MANAGEMENT INTERFACE TIMING................................................. 18 INTRODUCTION.......................................................................................................... 19 High Performance Analog................................................................................... 19 Low Power Consumption.................................................................................... 19 Application Flexibility........................................................................................... 19 Typical Connection Diagram............................................................................... 19 FUNCTIONAL DESCRIPTION.................................................................................... 21 Major Operating Modes....................................................................................... 21 100BASE-X MII Application (TX and FX)..................................................... 21 Symbol Encoding and Decoding........................................................... 22 100 Mb/s Loopback............................................................................... 23 100BASE-X Repeater Application............................................................... 23 10BASE-T MII Application........................................................................... 24 Full and Half Duplex operation.............................................................. 24 Collision Detection................................................................................. 24 Jabber................................................................................................... 24 Link Pulses............................................................................................ 24 Receiver Squelch.................................................................................. 25 10BASE-T Loopback............................................................................. 25 Carrier Detection................................................................................... 25

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

10BASE-T Serial Application....................................................................... 25 Auto-Negotiation................................................................................................. 25 Reset Operation.................................................................................................. 26 LED Indicators..................................................................................................... 26 MEDIA INDEPENDENT INTERFACE (MII)................................................................. 27 MII Frame Structure............................................................................................ 27 MII Receive Data................................................................................................. 28 MII Transmit Data................................................................................................ 28 MII Management Interface.................................................................................. 29 MII Management Frame Structure...................................................................... 29 CONFIGURATION...................................................................................................... 30 Configuration At Power-up/Reset Time............................................................... 30 Configuration Via Control Pins............................................................................ 30 Configuration via the MII..................................................................................... 30 CS8952 REGISTERS.................................................................................................. 31 Basic Mode Control Register - Address 00h..................................................... 32 Basic Mode Status Register - Address 01h...................................................... 34 PHY Identifier, Part 1 - Address 02h................................................................. 36 PHY Identifier, Part 2 - Address 03h................................................................. 37 Auto-Negotiation Advertisement Register - Address 04h.................................. 38 Auto-Negotiation Link Partner Ability Register - Address 05h........................... 39 Auto-Negotiation Expansion Register - Address 06h........................................ 40 Auto-Negotiation Next-Page Transmit Register - Address 07h......................... 41 Interrupt Mask Register - Address 10h............................................................. 42 Interrupt Status Register - Address 11h............................................................ 45 Disconnect Count Register - Address 12h........................................................ 48 False Carrier Count Register - Address 13h..................................................... 49 Scrambler Key Initialization Register - Address 14h......................................... 50 Receive Error Count Register - Address 15h.................................................... 51 Descrambler Key Initialization Register - Address 16h..................................... 52 PCS Sub-Layer Configuration Register - Address 17h..................................... 53 Loopback, Bypass, and Receiver Error Mask Register - Address 18h............. 56 Self Status Register - Address 59 10BASE-T Status Register - Address 61 10BASE-T Configuration Register - Address 1Ch............................................ 62 DESIGN CONSIDERATIONS...................................................................................... 64 Twisted Pair Interface......................................................................................... 64 100BASE-FX Interface........................................................................................ 64 Internal Voltage Reference................................................................................. 64 Clocking Schemes.............................................................................................. 65 Recommended Magnetics.................................................................................. 66 Power Supply and Decoupling............................................................................ 66 General Layout Recommendations..................................................................... 66 PIN DESCRIPTIONS................................................................................................... 69 PACKAGE DIMENSIONS........................................................................................... 81


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