CDC5801DBQ Datasheet

Low Jitter PLL Based Multiplier/divider With Programmable Delay Lines Down to Sub 10ps


Features, Applications

Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz Low Jitter Clock Divider /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency From 12.5 MHz to 62.5 MHz 2.6 mUI Programmable Bidirectional Delay Steps Typical 8.0-ps Phase Jitter (12 kHz to 20 MHz) @ 500 MHz Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) @ 500 MHz One Single-Ended Input and One Differential Output Pair Output Can Drive LVPECL, LVDS, and LVTTL Three Power Operating Modes to Minimize Power Low Power Consumption (Typical at 500 MHz) Packaged in a Shrink Small-Outline Package (DBQ) No External Components Required for PLL Spread Spectrum Clock Tracking Ability to Reduce EMI

REFCLK Terminal Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper VDDREF Voltage Level (For Example, HSTL 1.5 if VDDREF 1.6 V) Supports Industrial Temperature Range to 85�C


The CDC5801 device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz. Please see Table 1 and Table 2 for detail frequency support. The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals. The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit interval). For every rising edge on the DLYCTRL terminal the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly for every rising edge on the DLYCTRL terminal the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by or 8) with the phase aligner bypassed as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the VDDREF terminal. The CDC5801 device is characterized for operation over free-air temperatures to 85�C.

PLLCLK Phase Aligner Bypass MUX REFCLK PLL B Phase Aligner Divider Ratio CLKOUT CLKOUTB

FUNCTION TABLE MODE Multiplication with programmable delay and phase alignment active Division with programmable delay and phase alignment active Multiplication only mode (phase aligner bypassed) � Test mode P2 0 CLKOUT/CLKOUTB REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs are delayed or advanced based on DLYCTRL and LEADLAG terminal configuration. REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs are delayed or advanced based on DLYCTRL and LEADLAG terminal configuration. In this mode one can only multiply as per Table 1. Programmable delay capability and divider capability is deactivated. PLL is running. PLL and phase aligner both bypassed. REFCLK is directly channeled to output.

Hi-Z mode 1 X Hi-Z X = don't care, Hi-Z = high impedance Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions. � In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency.



Manufacturer information

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