Four CPU Clock Outputs With Programmable Frequency (50 MHz, 60 MHz, and 66 MHz) Six Clock Outputs at Half-CPU Frequency for PCI One 24-MHz Clock Output One 12-MHz Clock Output Two 14.318-MHz Reference Outputs All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input LVTTL-Compatible Inputs and Outputs Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components Operates at 3.3 VCC Distributed VCC and Ground Pins Reduce Switching Noise Packaged in Plastic Small-Outline Packagedescription
The is a high-performance clock synthesizer/driver that generates all required clock signals necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs (PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency of PCLKn and are delayed 4 ns from the rising edge of the CPU clock. In addition, the four fixed-frequency outputs provide a 24-MHz clock a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). The CDC9841 generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be provided at X1 instead of a crystal input. Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The PCI and 12-MHz clock frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can be bypassed in the TEST mode (i.e., H) to distribute a test clock provided at the X1 input. Because the CDC9841 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, as well as following any changes to the SELn inputs. PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are enabled via OE.
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FUNCTION TABLE X1 14.31818 MHz 14.31818 MHz 14.31818 MHz 14.31818 MHz TCLK PCLKn Hi-Z 50 MHz 60 MHz 66 MHz BCLKn Hi-Z 25 MHz 30 MHz 33 MHz TCLK /4 REFn Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz TCLK CLK24 Hi-Z 24 MHz 24 MHz 24 MHz TCLK /4 CLK12 Hi-Z 12 MHz 12 MHz 12 MHz TCLK /8H TCLK /2 TCLK is a test clock input at the X1 input during test mode.