CDCVF2505DR Datasheet

Clock Drivers & Distribution


The CDCVF2505DR is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0&minus;3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. CDCVF2505DR Features &bull; Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications&bull; Spread Spectrum Clock Compatible&bull; Operating Frequency: 24 MHz to 200 MHz&bull; Low Jitter (Cycle-cycle): <|150 ps| Over the Range 66 MHz&minus;200 MHz&bull; Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay)&bull; Three-States Outputs When There Is no Input Clock&bull; Operates From Single 3.3-V Supply&bull; Available in 8-Pin TSSOP and 8-Pin SOIC Packages&bull; Consumes Less Than 100 &mu;A (Typically) in Power Down Mode


[{"Name":"Supply Voltage - Max","Value":"3.6 V "},{"Name":"Supply Voltage - Min","Value":"3 V "},{"Name":"Maximum Operating Temperature","Value":"+ 85 C "},{"Name":"Package / Case","Value":"SOIC-8 "},{"Name":"Packaging","Value":"Reel"},{"Name":"Minimum Operating Temperature","Value":"- 40 C "},{"Name":"Mounting Style","Value":"SMD/SMT "}]

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