CDP1824 Datasheet

32-Word X 8-Bit Static RAM


Features, Applications


The CDP1824 and CDP1824C are x 8-bit fully static CMOS random-access memories for use in CDP-1800 series microprocessor systems. These parts are compatible with the CDP1802 microprocessor and will interface directly without additional components. The CDP1824 is fully decoded and does not require a precharge or clocking signal for proper operation. It has common input and output and is operated from a single voltage supply. The MRD signal (output disable control) enables the three-state output drivers, and overrides the MWR signal. A CS input is provided for memory expansion. The CDP1824C is functionally identical to the CDP1824. The CDP1824 has an operating range to 10.5V, and the CDP1824C has an operating voltage range to 6.5V. The CDP1824 and CDP1824C are supplied in 18 lead hermetic dual-in-line ceramic packages (D suffix), and in 18 lead dual-in-line plastic packages (E suffix).

Fast Access Time - VDD 710ns - VDD 320ns No Precharge or Clock Required
CDP1824D 10V PDIP Burn-In SBDIP to +85oC PACKAGE TEMPERATURE RANGE to +85oC PKG. NO. E18.3 D18.3

OPERATIONAL MODES CS MRD MWR DATA PINS STATUS Output: High/Low Dependent on Data Input: Output Disabled Output Disabled: High-Impedance State Output Disabled: High-Impedance State X = Don't Care

READ WRITE Not Selected Standby Logic 1 = High

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. 1 Copyright � Intersil Americas Inc. 2002. All Rights Reserved

DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) to +7V Input Voltage Range, All Inputs. -0.5V to VDD +0.5V DC Input Current, Any One Input. �10mA Operating Temperature Range (TA) Package Type to +125oC Package Type to +85oC

Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package. 75 20 PDIP Package. 75 N/A Storage Temperature Range to +150oC Lead Temperature (During Soldering) At distance � 1/32 In. � 0.79mm) from case for 10s max. +265oC

TA = Full Package Temperature Range.For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CONDITION CDP1824D LIMITS CDP1824CD MIN 4 VSS MAX 6.5 VDD 5 UNITS V �s

PARAMETER Supply Voltage Range Recommended Input Voltage Range Input Signal Rise or Fall Time (Note 1) tR, tF NOTE:

1. Input signal rise or fall times longer than these maxima can cause loss of stored data in either the selected or deselected mode.

to +85oC, Except as Noted: CONDITIONS CDP1824 LIMITS CDP1824C MAX MIN (NOTE 1) TYP MAX UNITS �A mA

PARAMETER Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage

to +85oC, Except as Noted: (Continued) CONDITIONS CDP1824 PARAMETER Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES: 1. Typical values are for = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1�s. SYMBOL IOUT VO (V) CIN COUT VIN (V) VDD (V) 5 10 MIN (NOTE 1) TYP MAX MIN LIMITS CDP1824C (NOTE 1) TYP MAX 7.5 15 UNITS �A pF

to +85oC, VDD �5%, Input tR, = 200k; See Figure 1 LIMITS CDP1824D, CDP1824E (NOTE 1) MIN (NOTE 2) TYP CDP1824CD, CDP1824CE (NOTE 1) MIN (NOTE 2) TYP

PARAMETER READ OPERATION Access Time From Address Change Access Time From Chip Select Output Active From MRD

NOTES: 1. Time required by a limit device to allow for the indicated function. 2. Time required by a typical device to allow for the indicated function. Typical values are for = +25oC and nominal VDD.


NOTES: 1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output. FIGURE 1. READ CYCLE TIMING DIAGRAMS



Manufacturer information

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