Dual N-Channel Enhancement Mode Field Effect Transistor
RDS(ON)=40m @VGS=2.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. TSSOP-8 for Surface Mount Package.
Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous a b -Pulsed Drain-Source Diode Forward Current a Maximum Power Dissipation a Operating Junction and Storage Temperature RangeABSOLUTE MAXIMUM RATINGS (TA=25 C unless otherwise noted)
Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage BVDSS IDSS IGSS VGS(th) RDS(ON) ID(ON) gFSDrain-Source On-State Resistance On-State Drain Current Forward Transconductance
Input Capacitance Output Capacitance Reverse Transfer Capacitance
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall time Total Gate Charge Gate-Source Charge Gate-Drain Charge
Notes a.Surface Mounted on FR4 Board, t 10sec. b.Pulse Test:Pulse Width 300s, Duty Cycle 2%. c.Guaranteed by design, not subject to production testing.