HomedatasheetCGS3314M

CGS3314M Datasheet

Clock Circuits
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Description

Features, Applications

The CGS3317, CGS3318 and CGS3319 devices are designed for Clock Generation and Support (CGS) applications to 110 MHz. The CGS331x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 331x devices provide selectable output divide ratio (and selectable crystal drive level). The circuit is designed to operate over a wide frequency range using fundamental model or overtone crystals.

Features

s Fairchild's CGS family of devices for high frequency clock source applications s Crystal frequency operation range: fundamental: 10 MHz to 100 MHz typical or 5th overtone: 10 MHz to 85 MHz s Programmable oscillator drive s Selectable fast output edge rates s Output symmetry circuit to adjust 50% duty cycle point between CMOS and TTL levels s Output current drive 48 mA for IOL/IOH s FACTTM CMOS output levels s Output has high speed short circuit protection s Basic oscillator type: Pierce s Hysteresis inputs to improve noise margin

Order Number CGS3318M CGS3319M Package Number Package Description M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Division Selection DIVB DIVA OEL 0/F OEH Divider Output X 0 Divide-by 1 Divide-by 2 Divide-by 4 Divide-by 8 Divide-by 16 Divide-by 32 Output Reset HIGH at Re-enable Output Reset HIGH at Re-enable OSC_DR 1 F Rise and Fall Time Selection OSC_DR DIV TRF Rise/Fall Time (ns) 1 2 less than

Note: Actual value of the floating OSC_DR and DIVB input is VCC/2

Note: Pin out varies for each device. OSC_IN Input to Oscillator Inverter. The output of the crystal would be connected here. OEL Active LOW 3-STATE enable pin. This pin pulls to a low value when left floating and 3-STATE the output when forced HIGH. This pin has TTL compatible input levels. Rise and Fall time override pin. Available only for die form. This pin is the main clock output on the device. The Oscillator LOW pin is the ground for the Oscillator. This pin is the same signal OSCLO_1. It has been provided as an alternate connection for OSCLO_1 for hybrid assemblies. The power pin for the chip. The ground pin for all sections of the circuitry except the oscillator and oscillator related circuitry.

OSC_OUT Resistive Buffered Output of the Oscillator Inverter OSC_DR DIVA OEH 3 Level input pin that selects Oscillator Drive Level Input used to select Binary Divide-by Option. This pin has CMOS compatible input levels.

Active HIGH 3-STATE enable pin. This pin pulls to a high value when left floating and 3-STATEs the output when forced low. This pin has TTL compatible input levels. VCC GND

Each drive has one output with the choices of selecting frequency divide, output enable, crystal drive and output rise and fall time. Crystal drive options are: L = LOW Drive M = MEDIUM Drive H = HIGH Drive


Features

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Manufacturer information

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