The is a multifunction chip which integrates a LO time two multiplier, a balanced cold FET mixer, and a RF LNA. It is designed for a wide range of applications, typically commercial communication systems. The backside of the chip is both RF and DC grounds. This helps simplify the assembly process. The circuit is manufactured with a PM-HEMT process, 0.25�m gate length, via holes through the substrate, air bridges and electron beam gate lithography. It is available in chip form.
Broadband performances 11 dB conversion gain 3.5.0dB noise figure 10dBm LO input power -10dBm RF input power (1dB gain comp.) Low DC power consumption, 120mA@3.5V Chip size 0.10 mmConversion Gain & Image suppression @ IF=1.5GHz (including test board losses)
RF frequency range LO frequency range IF frequency range Conversion gain
ESD Protection : Electrostatic discharge sensitive device. Observe handling precautions !
Ref. -20-July-01 1/6 Specifications subject to change without notice
RF frequency range LO frequency range IF frequency range Conversion gain (1) Noise Figure LO Input power Image Suppression Input power at 1dB gain compressionLO VSWR Input LO VSWR (1) RF VSWR Input RF VSWR (1) Id Bias current (2)
(1) On Wafer measurements (2) Current source biasing network is recommended. Optimum performances for Idm= 50mA and Idl= 70mA
Id Vg Pin Ta Tstg Drain bias voltage Drain bias current Gate bias voltage Maximum peak input power overdrive (2) Operating temperature range Storage temperature range
(1) Operation of this device above anyone of these parameters may cause permanent damage. (2) Duration < 1s.Bias Conditions : Vdm= Vdl= 3.5 V, Vgm= -0.9V, Vgb= -0.3V, Vgx= -0.7V, Vga= -0.2V
Ref. -20-July-01 3/6 Specifications subject to change without notice
Freq_RF= 28GHz Freq_LO= 13.75GHz IF power_I (dBm) IF power_Q (dBm) Conv_gain I (dB) Conv_gain Q (dB)