The is a high-speed 2:1 multiplexer with active input and output stages. The CLC532 also employs a closed-loop design which dramatically improves accuracy. This monolithic device is constructed using an advanced high-performance bipolar process. The CLC532 has been specifically designed to provide settling times to 0.01%. This, coupled with the adjustable noise-bandwidth, makes the CLC532 an ideal choice for infrared and CCD imaging systems. Channel-to-channel isolation is better than @ 10MHz. Low distortion (80dBc) and spurious signal levels make the CLC532 a very suitable choice for both I/Q processors and receivers. The CLC532 is offered over both the industrial and military temperature ranges. The Industrial versions, CLC532AJP\AJE\AID, are specified from to +85�C and are packaged in 14-pin plastic DIP's, 14-pin SOIC's and 14-pin Side-Brazed packages. The extended temperature versions, CLC532A8B/A8D/A8L-2, are specified from to +125�C and are packaged a 14-pin hermetic DIP and 20-terminal LCC packages. (Contact factory for LCC and CERDIP availability.) Ordering Information...
CLC532A8B 14-pin plastic DIP 14-pin plastic SOIC dice dice, MIL-STD-833 14-pin CERDIP; MIL-STD-883 20-terminal LCC; +125oC MIL-STD-883 Contact factory for other packages and DESC SMD number. +85oC +125oCFeatures
12-bit settling - 17ns Low noise - 32�Vrms High isolation @ 10MHz Low distortion @ 5MHz Adjustable bandwidth - 190MHz (max) Infrared system multiplexing CCD sensor signals Radar I/Q switching High definition video HDTV Test and calibrationApplications
FREQUENCY DOMAIN PERFORMANCE -3dB bandwidth -3dB bandwidth gain flatness peaking rolloff linear phase deviation differential gain differential phase crosstalk rejectionTIME DOMAIN PERFORMANCE rise and fall time settling time 2V step; from 50% VOUT
overshoot slew rate SWITCH PERFORMANCE channel to channel switching time (2V step at output) switching transient
DISTORTION AND NOISE PERFORMANCE 2nd harmonic distortion 5MHz 3rd harmonic distortion 2Vpp, 5MHz equivalent input noise spot noise voltage >1MHz integrated noise to 100MHz spot noise current STATIC AND DC PERFORMANCE * analog output offset voltage temperature coefficient analog output offset voltage matching * analog input bias current temperature coefficient analog input bias current matching analog input resistance analog input capacitance * gain accuracy gain matching integral endpoint non-linearity output voltage output current output resistance DIGITAL INPUT PERFORMANCE ECL mode (pin 6 floating) input voltage logic HIGH input voltage logic LOW input current logic HIGH input current logic LOW TTL mode (pin = +5V) input voltage logic HIGH input voltage logic LOW input current logic HIGH input current logic LOW POWER REQUIREMENTS * supply current (+VCC +5.0V) * supply current (-VEE = -5.2V) nominal power dissipation * power supply rejection ratio
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
positive supply voltage (+VCC) negative supply voltage (-VEE) differential voltage between any two GND's analog input voltage range SELECT input voltage range (TTL mode) SELECT input voltage range (ECL mode) CCOMP range2 thermal data 14-pin plastic 14-pin Cerdip 14-pin SOIC 20-terminal LCC JC (�C/W) JA (�C/W) to 100pF
positive supply voltage (+VCC) negative supply voltage (-VEE) differential voltage between any two GND's analog input voltage range digital input voltage range output short circuit duration (output shorted to GND) junction temperature operating temperature range CLC532AJP/AJE/AIB storage temperature range lead solder duration (+300� C) ESD rating transistor count -7.0V 200mV -VEE to +VCC -VEE to +VCC Infinite C 10 sec <500V 74Note 2: The CLC532 does not require external C COMP capacitors for proper operation.
Note 3: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.SETTLING ERROR WINDOW A SELECT SWT10 90% OUTPUT 10% CHANNEL = +1V CHANNEL = -1V TRx TSx TRx