CLC5958SLB Datasheet

14-bit, 52msps A/D Converter


Features, Applications

The is a monolithic 14-bit, 52 MSPS analog-to-digital converter. The ultra-wide dynamic range and high sample rate of the device make it an excellent choice for wideband receivers found in multi-channel base-stations. The CLC5958 integrates a low distortion track-and-hold amplifier and a 14-bit multi-stage quantizer on a single die. Other features include differential analog inputs, low jitter differential clock inputs, an internal bandgap voltage reference, and CMOS/TTL compatible outputs. The CLC5958 is fabricated on the National ABIC-V 0.8 micron BiCMOS process. The CLC5958 features 90 dB spurious free dynamic range (SFDR) and 70 dB signal-to-noise ratio (SNR). The balanced differential analog inputs ensure low even-order distortion, while the differential clock inputs permit the use of balanced clock signals to minimize clock jitter. The 48-pin CSP package provides an extremely small footprint for applications where space is a critical consideration. The package also provides a very low thermal resistance to ambient. The CLC5958 may be operated with a single +5V power supply. Alternatively, an additional supply may be used to program the digital output levels over the range to +5V. Operation over the industrial temperature range +85�C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications.


Ultra-wide dynamic range Excellent performance to Nyquist IF sampling capability Very small package: 48-pin CSP Programmable Output Levels: to 5V

n Sample Rate n SFDR n Noise floor 52 MSPS dB -72 dBFS

n Multi-channel basestations n Multi-standard basestations: GSM, WCDMA, DAMPS, etc. n Smart antenna systems n Wireless local loop n Wideband digital communications

Pin Name AIN, AIN ENCODE, ENCODE Pin No. 13, 14 Description Differential inputs. Self biased at a common mode voltage of +3.25V. The ADC full scale input is 2.048 VPP differential. Differential clock inputs. ENCODE initiates a new data conversion cycle on each rising edge. Clock signals may be sinusoidal or square waves with PECL encode levels. The falling edge of ENCODE clocks internal pipeline stages. Digital data outputs. CMOS and TTL compatible. D0 is the LSB and D13 is the inverted MSB. Output coding is two's complement. Data valid. The rising edge of this signal occurs when output data is valid and may be used to latch data into following circuitry. Internal analog input common mode voltage reference. Nominally +3.25V. Can be used to establish the analog input common mode voltage for DC coupled applications (DC coupling not recommended, see applications section). Circuit ground. +5V power supply. Bypass each group of supply pins to ground with 0.01 �F capacitor. to +5V power supply for the digital outputs. Establishes the high output level for the digital outputs. Bypass to ground with 0.1 �F capacitor.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (VCC) Differential Voltage between any Two Grounds Analog Input Voltage Range Digital Input Voltage Range Output Short Circuit Duration (one-pin to ground) Junction Temperature Storage Temperature Range Lead Solder Duration (+240�C) ESD tolerance human body model machine model to +6V

Positive Supply Voltage (VCC) Analog Input Voltage Range Input Coupling Operating Temperature Range Digital Output Supply Voltage (DVCC) Analog Input Common Mode Voltage Package Thermal Resistance Package 48-Pin CSP 5% 2.048 VPP diff. � 5% VCM � 0.025V

The following specifications apply for VCC = +5V, DVCC +3.3V, 52 MSPS. Boldface limits apply for TA = Tmin -40�C to Tmax = +85�C, all other limits = 25�C (Note 4). Symbol Parameter RESOLUTION (Note 2) (Note 3) DIFFERENTIAL INPUT VOLTAGE RANGE MAXIMUM CONVERSION RATE (Note 2) (Note 3) SNR SFDR Signal-to-Noise Ratio (Note 2) Spurious-Free Dynamic Range (Note 2) SFDR Excluding 2nd and 3rd Harmonics (Note 2) NO MISSING CODES (Note 2) NOISE AND DISTORTION Noise Floor (Note 6) fIN = 5 MHz, AIN = -1 dBFS fIN = 5 MHz, AIN = -20 dBFS 2nd and 3rd Harmonic Distortion (w/o fIN = 5 MHz, AIN = -1 dBFS dither) fIN = 20 MHz, AIN = -1 dBFS fIN = 70 MHz, AIN -3 dBFS Next Worst Harmonic Distortion (w/o dither)(Note 7) Worst Harmonic Distortion (with dither) (Note 8) fIN = 5 MHz, AIN = -1 dBFS fIN = 20 MHz, AIN = -1 dBFS fIN = 70 MHz, AIN -3 dBFS fIN = 5 MHz, AIN = -6 dBFS fIN = 20 MHz, AIN = -6 dBFS fIN = 70 MHz, AIN -6 dBFS fIN = 70 MHz (2 and 3 excluded), AIN -6 dBFS IMD SINAD 2-Tone IM Distortion (w/o dither) Signal-to-Noise and Distortion (w/o dither) fs/8, fs/4



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