CLC730075 - DIP packages Uses all through-hole components CLC730074 - SOIC packages Uses all surface-mount components
The CLC730075 and CLC730074 evaluation boards are designed to aid in the characterization of National Semiconductor's 14-pin, triple monolithic amplifiers.
Inverting Gain Operation The evaluation boards can be modified to provide an inverting gain configuration. Complete these steps to modify the board: 1. Cut the input trace 2. Use 25 for Rin 3. Terminate Rg at the input trace instead of ground 4. Add Rt for desired input impedance (input impedance = Rg||Rt) Figure 2 illustrates the inverting schematic for both boards.
Both boards have identical circuit configurations and are designed for non-inverting gains. Inverting gains or other circuit configurations can be obtained with slight modifications to the boards. Use the evaluation boards as a:Guide for high frequency layout Tool to aid in device testing and characterization
Basic Operation Figure 1 shows the non-inverting schematic for both boards. The input signal is brought into the board through SMA connectors to the non-inverting input of the amplifier. The resistor Rin is used to set the input termination resistance to the op amp. The noninverting gain is set by the following equation: Non-inverting Gain: Rf RgC4 -VCC Select Rt to yield desired input impedance = Rg||Rt
The value of the feedback resistor, Rf, has a strong influence on AC performance. Refer to the product data sheet for feedback resistor selection. The output of the op amp travels through a series resistance, Rout, and then leaves the board through an SMA connector. The series resistance, Rout, matches transmission lines or isolates the output from capacitive loads. The 0.1�F capacitor, C5, is placed between the power pins of the amplifier to improve harmonic distortion performance. C5 is placed directly across pins 4 and 11, refer to the CLC730074 board, then the capacitor provides the best improvement in distortion performance.
Figure 2: Inverting Gain Configurations Isolation and Channel Matching Performance For maximum isolation between channels, proper power supply decoupling is required. Always include the bypass capacitors C2, C3, and C4. The use of good quality capacitors also helps to achieve better isolation performance. The evaluation boards have also been designed to minimize channel-to-channel crosstalk. The input and output pins of the amplifier are sensitive to the coupling of parasitic capacitances caused by power or ground planes and traces. To reduce the influence of these parasitics, the ground plane has been removed around these sensitive nodes. In multilayer boards, remove both the ground and power traces and planes around the input and output pins. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. When designing your own board, use the evaluation board as a guide and follow these steps as a basis for high frequency layout: 1. Use a ground plane. 2. Include 6.8�F tantalum and 0.1�F ceramic capacitors on both supplies.
3. Place the 6.8�F capacitors within 0.75 inches of the power pins. 4. Place the 0.1�F capacitors less than 0.1 inches from the power pins. 5. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. 6. Minimize all trace lengths to reduce series inductances. 7. Use individual flush-mount sockets, for prototyping. Measurement Hints If 50 coax and 50 Rin/Rout resistors are used, many of the typical performance plots found in the product data sheets can be reproduced. When SMA connectors and cables are not available to evaluate the amplifier, do not use normal oscilloscope probes. Use low impedance resistive divider probes If a low impedance probe is not available, then a section of 50 coaxial cable and a low impedance resistor to 50) may be used. Follow these 3 steps to create a "cable/resistor" probe: 1. Connect one end of the coax's center to a test measurement box terminated 50. 2. Connect the other end of the cable's center conductor to the low impedance resistor. (The open side of the resistor is now a probe.) 3. Connect the ground shield of the cable to evaluation board ground and test box ground.
Figure 3: "Cable/Resistor" Probe Configuration This "cable/resistor" probe, shown in Figure 3, forms a voltage attenuator between the resistor and the 50 termination resistance of the test box. This method allows measurements to be performed directly on the output pin of the amplifier. When evaluating only one channel on the board, complete the following on the unused channel: 1. Included Rf and Rg as shown in Figure 1 2. Ground the input 3. Load the output with 50 to ground Power Supplies Refer to the product data sheet for the recommended supply voltages. Component Values s Rf, Rg - Use the product data sheet to select values s Rin, Rout - 50 (Refer to Basic Operation section for details) Rt - Optional resistor for inverting gain configurations (Refer Inverting Gain Operation section for details) - 6.8�F tantalum capacitors - 0.1�F ceramic capacitors